Senior Synthesis & Timing Engineer (ASIC/FPGA)

Roguebeam; Seattle (WA); On-site; USD 150,000 - 210,000; Full time

Job summary

Roguebeam, a Seattle-based startup, is seeking a Senior Synthesis / Timing Engineer to own constraints, RTL synthesis, and static timing for ASIC/FPGA solutions. You will bridge algorithm RTL to a timing-clean netlist, enabling high-throughput beamforming and low-power data paths.

You’ll lead end-to-end flows: SDC, multi-mode constraints, synthesis, STA, ECO loops, and collaboration with DSP/RTL and PD teams to deliver timing-credible designs for in-house phased-array systems.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 7–10 years of relevant experience in synthesis and STA for ASICs or large FPGAs.
• Strong hands-on experience with industry tools (e.g., Design Compiler / Fusion Compiler / Genus, PrimeTime or Tempus)
• Proven production-quality SDC, multi-mode multi-corner timing closure, and ECO methodology
• Solid RTL literacy (SystemVerilog/Verilog) and ability to work with DSP-heavy, high-utilization designs
• Demonstrated ability to translate performance requirements into implementable constraints and closed timing

Responsibilities

• Own synthesis flows and SDC for DSP data paths, beamforming engines, control logic, and high-speed interfaces.
• Run and sign off STA (including OCV/AOCV as applicable); analyze critical paths, SI, and margin
• Drive timing and functional ECO loops with RTL and physical design; verify with formal (LEC) and STA
• Partner with DSP/RTL on architecture trade-offs (throughput, latency, area, power) and with DFT on scan/test clocks
• Support lint, CDC, and synthesis-clean RTL; feed PD with constraints, floorplan guidance, and timing budgets
• Support FPGA and ASIC lab bring-up when timing or constraints are implicated
• Contribute to technical strategy, design reviews, documentation, and mentoring as the team grows

Skills

RTL literacy

Synthesis & STA

Timing closure

EDA tools

Education

Bachelors in Electrical/Computer Engineering

MSc or PhD in VLSI/related field

Tools

Design Compiler

Fusion Compiler

Genus

PrimeTime/Tempus

Job description

Roguebeam, a Seattle-based startup, is seeking a Senior Synthesis / Timing Engineer to own constraints, RTL synthesis, and static timing for ASIC/FPGA solutions. You will bridge algorithm RTL to a timing-clean netlist, enabling high-throughput beamforming and low-power data paths.

You’ll lead end-to-end flows: SDC, multi-mode constraints, synthesis, STA, ECO loops, and collaboration with DSP/RTL and PD teams to deliver timing-credible designs for in-house phased-array systems.