Test Engineer

OTT Consulting Group; Sunnyvale (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

OTT Consulting Group in Sunnyvale, CA is seeking a DFT Engineer to design and implement comprehensive DFT architectures for next-generation SoC/ASIC designs. You will drive scan insertion, MBIST integration, and ATPG pattern generation while validating timing and power.

You’ll also transform patterns for ATE deployment and support post-silicon bring-up. The role requires hands-on Verilog/SystemVerilog expertise, strong experience with JTAG and 1149.x, and familiarity with DFT tools.

Qualifications

• Hands-on DFT experience in advanced SoC/ASIC development nodes.
• Strong proficiency in Verilog/SystemVerilog for DFT integration and simulation debugging.

Responsibilities

• Define and implement DFT architectures including Scan, ATPG, MBIST, and JTAG per IEEE standards.
• Perform Scan Chain Insertion, stitching, and optimization for timing closure and power grid compatibility.
• Integrate MBIST controllers, repair mechanisms, and custom memory test routines.
• Generate high-coverage ATPG patterns (Stuck-at, At-Speed, Cell-Aware)
• Simulate gate-level DFT to validate timing and vector cleanliness (SDF)
• Run DFT linting and rule checks with SpyGlass DFT, Tessent, Modus, or TetraMAX
• Translate ATPG/MBIST patterns to tester formats (WGL, STIL) for ATE deployment
• Support post-silicon bring-up and debugging of first-silicon DFT features
• Collaborate with Product and Test Engineering to optimize test time and yield

Skills

Verilog/SystemVerilog

Scan Insertion

ATPG

MBIST

JTAG (IEEE 1149.x)

Post-Silicon Support

Scripting (Tcl/Python/Perl)

STA/Timing Analysis

Tools

SpyGlass DFT

Tessent

Modus

TetraMAX

Synthesis tools (Synopsys Cadence)

Job description

• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG / IEEE standards (1149.1, 1500, 1687 IJTAG).
• Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and power grid compatibility.
• Integrate Memory BIST (MBIST) controllers, repair mechanisms, and custom memory test routines.
• Generate high-coverage Automatic Test Pattern Generation (ATPG) patterns, including Stuck-at, At-Speed (Transition/Path Delay), and Cell-Aware testing.
• Execute Verilog/SystemVerilog simulations for gate-level DFT validation, ensuring timing and vector cleanliness (SDF simulation).
• Run DFT linting and rule checking using industry-standard tools (e.g., SpyGlass DFT, Tessent, Modus, or TetraMAX)
• Translate pre-silicon ATPG and MBIST patterns into tester formats (e.g., WGL, STIL) for ATE (Automatic Test Equipment) deployment.
• Support post-silicon bring-up in the lab, debugging first-silicon DFT features, pattern conversion, and silicon failures.
• Collaborate with Product and Test Engineering (PTE) teams to optimize test time, diagnose failure modes, and boost manufacturing yield.

Required Qualifications:

Experience: 3+ years of hands-on DFT experience in advanced SoC/ASIC development nodes.

Core Skills & Technical Expertise: Verilog / SystemVerilog: Strong proficiency in Hardware Description Languages for DFT integration, wrapper creation, and simulation debugging.

Scan Insertion: Hands-on experience with scan synthesis, compressed scan architectures (EDT/SmartTest), and boundary scan integration.

ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.

• MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
• JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.
• Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.

Preferred Skills

Familiarity with scripting languages (Tcl, Python, or Perl) for automation of DFT flows.

Knowledge of advanced DFT concepts like High-Speed IO testing, SerDes loopback, or Analog DFT.

Understanding of synthesis tools (Synopsys Design Compiler, Cadence Genus) and static timing analysis (STA) constraint creation for DFT modes.