Principal DFT Engineer, HBM

Jobtailor; California (MO); On-site; USD 140,000 - 200,000; Full time

Job summary

Jobtailor seeks a senior DFT engineer in the United States to own SoC-level DFT implementation including scan, MBIST, LBIST, and JTAG-based test access for advanced ASICs.

You will drive DFT architecture early in the design cycle, collaborating with RTL, physical design, and integration teams, performing signoff and supporting pre- and post-silicon debug and yield analysis. Requires 7+ years in SoC/ASIC DFT and strong EDA tool experience.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of proven experience in SoC development, DFT, or implementation for complex digital ASICs or SoCs.
• Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
• Familiarity with RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design.
• Proficiency with industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
• Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation.

Responsibilities

• Own SoC-level DFT implementation including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base-die designs.
• Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints.
• Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams.
• Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff.
• Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis.

Skills

SoC Development

DFT Implementation

Scan Insertion

ATPG Concepts

EDA Tools Proficiency

Scripting Languages

Education

Bachelor’s degree or higher in Electrical/Computer Engineering

Tools

EDA Tools

Siemens Tools

Synopsys Tools

Cadence Tools

Job description

• Own SoC-level DFT implementation including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base-die designs
• Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints
• Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams
• Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure
• Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff
• Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis

Requirements

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field
• 7+ years of proven experience in SoC development, DFT, or implementation for complex digital ASICs or SoCs
• Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts
• Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design
• Proficiency with industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation
• Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation

Core Competencies

Demonstrates expertise in SoC-level DFT implementation, including scan, MBIST, LBIST, and JTAG, while ensuring alignment with design constraints. Proficient in collaborating with cross-functional teams to optimize DFT solutions and support pre-silicon and post-silicon processes.

Highest-signal resume keywords

• SoC Development
• DFT Implementation
• Scan Insertion
• ATPG Concepts
• EDA Tools Proficiency

ATS Optimization Keywords

Hard Skills

• DFT Logic Integration
• Scan Insertion
• MBIST Architecture
• LBIST Architecture
• Boundary Scan
• ATPG Readiness
• Full RTL-to-GDS Flows
• Scripting Languages
• DFT Rule Checks
• Coverage Closure

Industry Keywords

• Electrical Engineering
• Computer Engineering
• Digital ASICs
• SoCs
• Physical Design
• Timing Closure
• DRC
• LVS

Tools & Technologies

• EDA Tools
• Siemens Tools
• Synopsys Tools
• Cadence Tools