ASIC DFT Engineer

Jobtailor; California (MO); On-site; USD 130,000 - 190,000; Full time

Job summary

Jobtailor is seeking an experienced Hardware DFT Engineer to lead test-data path development for ASIC devices, collaborating across design, verification, and manufacturing teams to ensure robust in-system test and diagnostics from concept to post‑silicon validation.

You will own DFT IP development, implement features for JTAG, boundary scan and memory BIST, validate with ATPG tools, work with gate-level simulation (VCS) and ATE patterns (P1687), and mentor peers while driving technical

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• At least 5 years of experience in DFT, test and silicon engineering.
• Experience with JTAG protocols, scan and BIST architectures, including memory BIST and boundary scan.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent, PrimeTime.
• Experience with gate level simulation and debugging with VCS and other simulators.
• Post-silicon validation and debug experience.
• Ability to work with ATE patterns, P1687.

Responsibilities

• Implement DFT features to support ATE, in-system test, debug and diagnostics.
• Develop innovative DFT IP with cross-functional teams.
• Enable integration and validation of test logic in all implementation and post-silicon validation phases.
• Contribute to hardware DFT and physical design for new silicon models, bare and stacked dies.
• Craft solutions and debug with minimal mentorship.

Skills

DFT Implementation

Test Logic Integration

Gate Level Simulation

Debugging with VCS

Memory BIST

Boundary Scan

ATE Patterns

P1687

Innovative DFT Development

Silicon Engineering

Education

Bachelor's degree in Electrical Engineering

Master's degree in Computer Engineering

Tools

TestMax

Tetramax

Tessent

PrimeTime

VCS

Job description

Responsibilities

• Implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
• Development of innovative DFT IP in collaboration with the multi-functional teams
• Enabling the integration and validation of the test logic in all phases of the implementation and post‑silicon validation flows
• Participating in the creation of innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die
• Crafting solutions and debugging with minimal mentorship

Requirements

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required
• At least 5 years of experience
• Prior experience working in the latest innovative trends in DFT, test and silicon engineering
• Experience with JTAG protocols, scan and BIST architectures, including memory BIST and boundary scan
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Experience working with gate level simulation, debugging with VCS and other simulators
• Post-silicon validation and debug experience
• Ability to work with ATE patterns, P1687

Hard Skills

• DFT Implementation
• Test Logic Integration
• Gate Level Simulation
• Debugging with VCS
• Memory BIST
• Boundary Scan
• ATE Patterns
• P1687
• Innovative DFT Development
• Silicon Engineering

Soft Skills

• Collaboration
• Problem‑Solving
• Minimal Mentorship

Certifications & Qualifications

• Bachelor's Degree in Electrical Engineering
• Master's Degree in Computer Engineering