Tech Lead - Design Verification for AI Connectivity

Asteralabs; San Jose (CA); On-site; USD 175,000 - 195,000; Full time

Job summary

Astera Labs is seeking a Tech Lead Engineer, Design Verification to define and deliver robust verification for next-generation connectivity silicon for rack-scale AI infrastructure. You will partner with RTL, architecture, firmware, and post-silicon teams to build verification strategies proving high-bandwidth protocol behavior.

In CCE2, lead verification challenges from planning to coverage closure, contributing to reliable PCIe and UALink connectivity products enabling AI accelerators, memory,

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 5–8 years of design verification experience for ASICs/SoCs.
• Hands-on SystemVerilog and UVM-based verification.
• Experience creating verification plans, testbenches, assertions, scoreboards, and coverage models.
• Familiarity with simulation, waveform debugging, regression and coverage tools.

Responsibilities

• Develop verification strategy and planning for RTL and features.
• Build and enhance UVM-based testbenches, sequences, monitors, and reference models.
• Define test scenarios, coverage models, checkers, and scoreboards for complex switching functionality.
• Lead verification planning, risk tracking, and milestone achievement.
• Debug simulation failures using waveform analysis and cross‑functional collaboration.
• Communicate verification status, risks and recommendations to stakeholders.

Skills

SystemVerilog

UVM

Debugging

Leadership

Communication

Python

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Job description

Astera Labs is seeking a Tech Lead Engineer, Design Verification to define and deliver robust verification for next-generation connectivity silicon for rack-scale AI infrastructure. You will partner with RTL, architecture, firmware, and post-silicon teams to build verification strategies proving high-bandwidth protocol behavior.

In CCE2, lead verification challenges from planning to coverage closure, contributing to reliable PCIe and UALink connectivity products enabling AI accelerators, memory,