Tech Lead, RTL/SoC Design for AI Connectivity

Astera Labs; San Jose, Northern (CA, KY); Hybrid; USD 160,000 - 200,000; Full time

Job summary

Astera Labs in San Jose, CA is seeking a Tech Lead Design Engineer to architect and deliver the connectivity silicon powering AI infrastructure. You will own RTL design for critical blocks from microarchitecture through synthesis, collaborating with architecture, verification, DFT and physical design teams.

The role emphasizes leadership, design methodology, and pre/post-silicon debugging, with opportunities to influence tapeout schedules and chip performance.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of digital design experience, including at least one full chip from spec to tapeout
• Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
• Hands-on experience with timing closure, CDC, lint, and low-power design techniques
• Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration

Responsibilities

• Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
• Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA
• Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality
• Partner with architecture to translate specifications into implementation-ready microarchitecture
• Collaborate with verification on testplans, coverage closure, and bug triage
• Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure
• Mentor junior engineers and contribute to design methodology, scripts, and best practices
• Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments
• Drive structured, data-driven design decisions in support of aggressive tapeout schedules

Skills

Verilog/SystemVerilog

RTL coding

Timing closure

High-speed interfaces

SoC integration

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

MS or PhD in Electrical Engineering or Computer Engineering

Job description

Astera Labs in San Jose, CA is seeking a Tech Lead Design Engineer to architect and deliver the connectivity silicon powering AI infrastructure. You will own RTL design for critical blocks from microarchitecture through synthesis, collaborating with architecture, verification, DFT and physical design teams.

The role emphasizes leadership, design methodology, and pre/post-silicon debugging, with opportunities to influence tapeout schedules and chip performance.