Lead Verification Architect - CXL/PCIe & Ethernet

Astera Labs; San Jose (CA); On-site; USD 185,000 - 230,000; Full time

Job summary

Astera Labs is seeking a Principal / Senior Principal Design Verification Engineer to lead verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. You will architect scalable UVM environments, mentor teams, and collaborate with architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.

Salary range $185,000–$230,000 with potential bonus.

Qualifications

• Bachelor's or Master's in Electrical/Electronic/Computer Engineering or related field.
• 10+ years (Principal) or 15+ years (Senior Principal) in Design Verification.
• Strong SystemVerilog and UVM expertise.
• Experience with verification planning, execution, and sign-off.
• Proficiency with SVA, functional coverage, and protocol compliance.
• Experience with industry-standard simulators: VCS, Xcelium, Questa.

Responsibilities

• Lead verification strategy for complex IPs and SoCs from architecture through silicon.
• Define reusable verification frameworks and best practices across programs.
• Drive verification planning, coverage closure, and sign-off.
• Identify risks early and drive mitigation plans.
• Mentor verification engineers and establish engineering excellence.

Skills

SystemVerilog

UVM

Verification planning

Constrained-random

Coverage-driven

SVA

Debugging RTL

Verification

Education

Bachelor's or Master's in EE/EC/CE or related

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

Astera Labs is seeking a Principal / Senior Principal Design Verification Engineer to lead verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. You will architect scalable UVM environments, mentor teams, and collaborate with architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.

Salary range $185,000–$230,000 with potential bonus.