Synthesis & Timing AI Engineer

Voltai; United States; On-site; USD 140,000 - 210,000; Full time

Job summary

Voltai is seeking a senior RTL/STA engineer to own the path from RTL to timing-clean netlist and to close timing for real silicon programs. You will help Voltai's AI learn to write constraints, diagnose violations, and improve timing accuracy.

You will work with design teams to drive synthesis, timing closure, and sign-off using industry-standard tools, while evaluating AI-assisted design approaches to improve reliability and flow efficiency.

Qualifications

• 5+ years of synthesis and STA experience on production tapeouts.
• Strong SDC skills: clocks, generated clocks, exceptions, multi-mode constraints.
• Experience with RTL-to-netlist flow and timing closure across corners and modes.

Responsibilities

• Own logic synthesis and constraint development (SDC) for blocks and full chips.
• Drive timing closure across corners and modes with RTL and physical design teams.
• Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis.
• Perform logic equivalence checking between RTL and netlist.
• Build automation to speed up synthesis and timing flows.
• Evaluate AI-generated constraints and timing fixes and help define good timing practices.

Skills

Synthesis/STA expertise

Tcl scripting

Python scripting

Tools

Design Compiler/Fusion Compiler

Genus

PrimeTime/Tempus

Formality/Conformal

Job description

Voltai is seeking a senior RTL/STA engineer to own the path from RTL to timing-clean netlist and to close timing for real silicon programs. You will help Voltai's AI learn to write constraints, diagnose violations, and improve timing accuracy.

You will work with design teams to drive synthesis, timing closure, and sign-off using industry-standard tools, while evaluating AI-assisted design approaches to improve reliability and flow efficiency.