RTL Design Engineer

Voltai; Palo Alto (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Voltai, a California-based company, seeks an experienced RTL design engineer to own microarchitecture and RTL for production silicon. You will drive the design flow from microarchitecture to signoff-ready code and collaborate with top semiconductor partners.

You’ll debug timing, run lint and CDC, and review AI-generated RTL to set the standard for high-quality design. You’ll interface with verification, backend teams, and customer design teams when needed.

Qualifications

• 5+ years of RTL design experience on chips that taped out.
• Expert SystemVerilog/Verilog and strong microarchitecture skills.
• Hands-on experience with lint, CDC, synthesis, and timing-aware design.

Responsibilities

• Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
• Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
• Partner with verification and formal teams on test plans, assertions, and coverage closure.
• Debug complex functional and timing issues across simulation, emulation, and silicon.
• Review and evaluate AI-generated RTL, and help define what correct, high-quality design looks like.
• Work directly with customer design teams when needed.

Skills

RTL design

SystemVerilog

Python scripting

Tcl scripting

Timing closure

PCIe or AXI

Tools

lint

CDC

synthesis

timing analysis

Job description

About Voltai

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

About Voltai

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

About The Team

Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

About This Role

You’ll design and own RTL for production silicon, from microarchitecture to signoff-ready code. You’ll work on real chip programs with leading semiconductor companies while helping Voltai's AI learn to write, review, and debug RTL the way the best designers do.

What You’ll Do

• Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
• Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
• Partner with verification and formal teams on test plans, assertions, and coverage closure.
• Debug complex functional and timing issues across simulation, emulation, and silicon.
• Review and evaluate AI-generated RTL, and help define what correct, high-quality design looks like.
• Work directly with customer design teams when needed.
  

What We’re Looking For

• 5+ years of RTL design experience on chips that taped out.
• Expert SystemVerilog/Verilog and strong microarchitecture skills.
• Hands-on experience with lint, CDC, synthesis, and timing-aware design.
• Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar).
• Python or Tcl scripting.
  

Bonus Points

• Experience writing SVA or working with formal verification.
• Low-power design (UPF, clock and power gating).
• Interest in AI-assisted design tools.