Synthesis & Static Timing Analysis (STA) Engineer

Voltai; Palo Alto (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Voltai is seeking an experienced IC design engineer to own the path from RTL to timing-clean netlist. You will close timing on silicon programs with leading semiconductor companies while helping Voltai's AI learn to write constraints and diagnose violations.

You will drive synthesis, timing closure, and STA analyses across corners and modes, and build automation to accelerate flows. Strong scripting and EDA tool experience are essential.

Qualifications

• 5+ years of synthesis and STA experience on production tapeouts.
• Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.
• Strong SDC skills: clocks, exceptions, generated clocks, and multi-mode constraints.
• Experience with logic equivalence checking (Formality or Conformal).
• Strong Tcl and Python scripting.

Responsibilities

• Own logic synthesis and constraint development (SDC) for blocks and full chips.
• Drive timing closure across corners and modes, working with RTL and physical design teams.
• Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis.
• Perform logic equivalence checking between RTL and netlist.
• Build automation that makes synthesis and timing flows faster and more reliable.
• Evaluate AI-generated constraints and timing fixes, and help define what good looks like.

Skills

Synthesis & STA

SDC constraints

Tcl scripting

Python scripting

Timing closure

Tools

Design Compiler

Fusion Compiler

Genus

PrimeTime

Tempus

Formality

Conformal

Job description

About Voltai

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

About Voltai

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

About The Team

Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

About This Role

You’ll own the path from RTL to a timing-clean netlist. You’ll close timing on real silicon programs with leading semiconductor companies while helping Voltai's AI learn to write constraints, diagnose violations, and close timing.

What You’ll Do

• Own logic synthesis and constraint development (SDC) for blocks and full chips.
• Drive timing closure across corners and modes, working with RTL and physical design teams.
• Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis.
• Perform logic equivalence checking between RTL and netlist.
• Build automation that makes synthesis and timing flows faster and more reliable.
• Evaluate AI-generated constraints and timing fixes, and help define what good looks like.

What We’re Looking For

• 5+ years of synthesis and STA experience on production tapeouts.
• Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.
• Strong SDC skills: clocks, exceptions, generated clocks, and multi-mode constraints.
• Experience with logic equivalence checking (Formality or Conformal).Strong Tcl and Python scripting.

Bonus Points

• Advanced node experience (7nm and below).
• Experience with ECO flows and timing signoff methodology.
• Interest in AI-assisted design tools.