Static Timing Analysis Engineer, Full-Chip STA

Google; Jasper (AL); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is seeking a Static Timing Analysis Engineer to own full-chip STA for SoCs in Mountain View, CA. You will implement timing signoff, optimize clock tree, and ensure energy and area goals.

Mid-level role requires 4 years of silicon timing experience, proficiency with PrimeTime/Tempus, and scripting in Tcl or Perl. You will collaborate with design, verification, and layout teams to drive silicon delivery.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 4 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and automation.
• Experience delivering silicon.

Responsibilities

• Deliver system-on-chip (SoC) Static Timing Analysis.
• Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
• Drive clock tree jitter and implementation for SoCs to achieve best energy, performance, and area.
• Execute full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing ECO creation, and oversee final timing signoff for SoCs.

Skills

Silicon timing closure

Scripting Tcl/Perl

Clock tree optimization

Education

Bachelor's degree in Electrical Engineering or Computer Science

Master's degree in Electrical Engineering or Computer Science

Tools

PrimeTime

Tempus

Job description

Static Timing Analysis Engineer, Full-Chip STA

Location: Mountain View, CA, USA

Experience Level: Mid

Mid experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

US: $138,000 - $197,000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Deliver system-on-chip (SoC) Static Timing Analysis.
• Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
• Drive clock tree jitter and implementation for SoCs to achieve best energy, performance, and area.
• Execute full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and oversee final timing signoff for SoCs.

Minimum qualifications

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 4 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
• Experience with Static Timing Analysis (STA) signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
• Experience delivering silicon.

Preferred qualifications

• Master's degree in Electrical Engineering or Computer Science.
• Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
• Experience with ASIC design flows and methodology of static timing analysis.
• Delivery of high-complexity silicon in state-of-the-art technology process nodes.
• Knowledge of semiconductor device physics and transistor characteristics.
• Effective skills with scripting languages such as Tcl or Perl.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

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