Static Timing Analysis Engineer, Full Chip STA

Google; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google seeks an experienced engineer to lead SoC Static Timing Analysis for complex silicon. You will define timing signoff, manage constraints, and optimize clocking for energy, performance, and area across full-chip designs.

The role emphasizes delivering high-complexity silicon, with experience in PrimeTime/Tempus and STA signoff for tapeouts, and collaboration with hardware teams to meet aggressive schedules.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
• Experience delivering silicon.

Responsibilities

• Be responsible for delivering system-on-chip (SoC) Static Timing Analysis (STA).
• Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
• Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance and area.
• Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoC’s.

Skills

ASIC design flows

Device physics knowledge

Deliver high complexity silicon

Tcl/Perl scripting

Education

Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience

Master's degree in Electrical Engineering, Computer Science, or a related field

Tools

PrimeTime

Tempus

STA signoff constraints tooling

Job description

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.

Minimum qualifications

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
• Experience delivering silicon.

Preferred qualifications

• Master's degree in Electrical Engineering, Computer Science, or a related field.
• Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
• Experience with ASIC design flows and methodology of static timing analysis.
• Knowledge of semiconductor device physics and transistor characteristics.
• Ability to deliver high complexity silicon in technology process nodes.
• Effective skills with scripting languages such as Tcl or Perl.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google.

• Be responsible for delivering system-on-chip (SoC) Static Timing Analysis (STA).
• Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
• Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance and area.
• Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoC’s.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.