Static Timing Analysis Engineer, Full Chip STA

Google; United States; Vor Ort; USD 163.000 - 236.000; Vollzeit

Benefits dieser Stelle

Equity

Benefits

Zusammenfassung

Google is seeking a Static Timing Analysis Engineer to own SoC STA for full-chip designs. Located in Mountain View, CA, you will work with PrimeTime and Tempus, define timing signoff processes, and drive clock-tree implementation to optimize energy, performance, and area.

The role emphasizes mentoring mid-level engineers and delivering high-complexity silicon. Responsibilities include full-chip STA, timing ECOs, and signoff oversight, with compensation including a strong base, 15% bonus target,

Qualifikationen

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
• Experience delivering silicon.

Aufgaben

• Deliver system-on-chip (SoC) Static Timing Analysis (STA).
• Define SoC timing signoff process corners, derates, uncertainties, and their tradeoffs.
• Drive clock tree jitter and implementation for SoCs to achieve best energy, performance, and area.
• Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation, and oversee final timing signoff for SoCs.

Kenntnisse

Tcl scripting

Perl scripting

SoC timing

Ausbildung

Bachelor's degree in EE/CS

Master's degree (preferred)

Tools

PrimeTime

Tempus

Jobbeschreibung

Static Timing Analysis Engineer, Full Chip STA

Location

• Mountain View, CA, USA

Experience Level

• Mid: Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.


• 8 years of technical experience in silicon timing closure and chip integration.


• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).


• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.


• Experience delivering silicon.

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Science, or a related field.


• Experience in extraction of design parameters, QoR metrics, and analyzing data trends.


• Experience with ASIC design flows and methodology of static timing analysis.


• Knowledge of semiconductor device physics and transistor characteristics.


• Ability to deliver high complexity silicon in technology process nodes.


• Effective skills with scripting languages such as Tcl or Perl.

About the Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163,000 - $236,000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Be responsible for delivering system-on-chip (SoC) Static Timing Analysis (STA).


• Define SoC timing signoff process corners, derates, uncertainties, and their tradeoffs.


• Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance, and area.


• Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation, and oversee final timing signoff for SoCs.

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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

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Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.