Mid-Level Full-Chip STA Engineer | Timing Signoff

Google Inc.; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google Inc. in Mountain View, CA seeks a Static Timing Analysis Engineer to own full-chip STA, drive clock tree timing, and ensure optimal performance for Google's devices. This role requires deep experience in silicon timing closure, signoff processes, and collaboration with SoC teams.

The candidate will work with PrimeTime/Tempus, build constraints, and mentor junior engineers. BS in EE/CS is required; a Masters is preferred. Salary ranges from USD 163,000 to 236,000 plus 15% bonus and equity.

Qualifications

• 8 years of technical experience in silicon timing closure and chip integration.
• Experience with full-chip timing signoff and STA tool automation.
• Bachelor's degree in Electrical Engineering or Computer Science.
• Experience with PrimeTime or Tempus.

Responsibilities

• Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
• Drive clock tree jitter and implementation for SoCs to achieve best energy, performance and area.
• Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs.

Skills

Timing closure

SoC integration

Scripting (Tcl/Perl)

Mentoring junior team

Education

Bachelor's degree in EE or CS

Master's degree (preferred)

Tools

PrimeTime

Tempus

Job description

Google Inc. in Mountain View, CA seeks a Static Timing Analysis Engineer to own full-chip STA, drive clock tree timing, and ensure optimal performance for Google's devices. This role requires deep experience in silicon timing closure, signoff processes, and collaboration with SoC teams.

The candidate will work with PrimeTime/Tempus, build constraints, and mentor junior engineers. BS in EE/CS is required; a Masters is preferred. Salary ranges from USD 163,000 to 236,000 plus 15% bonus and equity.