Staff SoC Layout/EDA Designer — RF & Analog Focus

Qorvo, Inc.; Fort Lauderdale (FL); On-site; USD 140,000 - 190,000; Full time

Job summary

Qorvo, Inc. is seeking a Staff SoC Layout/EDA Designer in Fort Lauderdale, FL to design and optimize complex chip layouts, collaborate with mixed-signal and digital teams, and drive tape-out readiness.

This professional role emphasizes flow automation, hierarchical verification, and mentoring junior designers. You will work across global teams to ensure specifications are met and production schedules are adhered to, leveraging Cadence Virtuoso, PDK tools, and PDk flows.

Qualifications

• 5+ years relevant industry work experience in layout design for SoCs
• Strong Cadence Virtuoso and PDK layout experience
• Proficient with physical verification flows (DRC, LVS, ERC, PERC) and tools like Pegasus/Calibre
• Knowledge of analog/RF/mixed-signal layout in sub-micron CMOS nodes
• Scripting ability (Linux shell, Makefile, TCL, Python) and AI-LLM client interactions

Responsibilities

• Collaborate with analog/RF/mixed-signal and digital engineers to create/optimize complex layouts for SoCs
• Automate layout workflows through scripting and batch operations
• Produce high quality macros and perform layout verification
• Own block-level layout designs and top-level floor planning with full hierarchical verification
• Lead layout flows, tape-out processes, and project database management
• Mentor junior layout designers and coordinate with global teams

Job description

Qorvo, Inc. is seeking a Staff SoC Layout/EDA Designer in Fort Lauderdale, FL to design and optimize complex chip layouts, collaborate with mixed-signal and digital teams, and drive tape-out readiness.

This professional role emphasizes flow automation, hierarchical verification, and mentoring junior designers. You will work across global teams to ensure specifications are met and production schedules are adhered to, leveraging Cadence Virtuoso, PDK tools, and PDk flows.