Senior SoC Layout/EDA Designer - Lead PNR & Tape-out

Skyworks Solutions, Inc.; Fort Lauderdale (FL); On-site; USD 109,000 - 227,000; Full time

Benefits offered by this job

Healthcare benefits

401(k) plan with company match

Employee stock purchase plan

Paid time off

Job summary

Skyworks Solutions, Inc. is seeking a Staff SoC Layout/EDA Designer in the United States. The role focuses on creating and optimizing layouts for complex blocks and chip-level macros, collaborating with analog/RF and digital teams.

You will drive automation of layout workflows, produce high-quality macros, and manage tape-out processes while mentoring junior designers and coordinating with global teams to meet specifications and schedules.

Qualifications

• Minimum of a Bachelor's degree in Electronic Engineering or related field.
• 8+ years of relevant industry work experience.
• Proficient with Cadence Virtuoso, PDK layouts, and physical verification flows.

Responsibilities

• Collaborate with analog/RF/mixed-signal and digital engineers to create and optimize layouts for complex blocks and SoC macros.
• Automate and customize layout workflows through scripting and batch operations.
• Produce high-quality analog/RF/mixed-signal macros and perform layout verification.
• Own block-level layout designs and top-level floor planning with full hierarchical verification.
• Lead layout design flows, document processes, and manage tape-out activities.
• Support layout contractors and mentor junior designers.
• Coordinate with global engineers to ensure timing and specification compliance.

Skills

Cadence Virtuoso

PDK layout tools

Pegasus/Calibre

DRC/LVS/ERC/PERC/LVL

Analog/RF/mixed-signal layout

CMOS 40nm or lower

LDE/ANT/ESD/LUP/NTN/TW/SOI concepts

Digital physical design (VHDL/Verilog/

LEF/DEF

Scripting (Linux shell, Makefile, TCL,

Python/AI-LLM clients

Education

Bachelor's degree in Electronic Engineering or related field

Job description

Skyworks Solutions, Inc. is seeking a Staff SoC Layout/EDA Designer in the United States. The role focuses on creating and optimizing layouts for complex blocks and chip-level macros, collaborating with analog/RF and digital teams.

You will drive automation of layout workflows, produce high-quality macros, and manage tape-out processes while mentoring junior designers and coordinating with global teams to meet specifications and schedules.