Staff SoC DFT Engineer — HBM Test Architecture

Micron Technology, Inc.; Town of Texas (WI); On-site; USD 120,000 - 170,000; Full time

Job summary

Micron Technology, Inc. is seeking an experienced design-for-test (DFT) engineer to own SoC-level DFT architecture and implementation for high‑bandwidth memory (HBM) base‑die designs. You will work with RTL, synthesis, STA, and physical design teams to ensure manufacturability and silicon bring‑up.

This role requires hands‑on DFT expertise (scan, MBIST/LBIST, boundary scan/JTAG, ATPG), strong collaboration across global teams, and a drive to innovate for future HBM generations.

Qualifications

• Strong hands-on experience with SoC design for test (DFT) architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
• Experience across RTL-to-GDS flows with synthesis, STA, and physical design collaboration.
• Proficiency with industry-standard EDA tools from Siemens, Synopsys, and Cadence for DFT and implementation.
• Bachelor's degree in Electrical or Computer Engineering or related field.

Responsibilities

• Own SoC-level DFT architecture and implementation for HBM base-die designs.
• Define and drive DFT architecture early in the design cycle with SoC integration in mind.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels with RTL/SoC teams.
• Execute and sign off DFT flows including ATPG readiness and coverage closure.
• Collaborate with physical design teams to optimize DFT for placement, routing, timing, and signoff.
• Coordinate with verification, product engineering, test, and manufacturing for testability and post-silicon bring-up.

Skills

SoC DFT architecture

Scan insertion

MBIST/LBIST

JTAG boundary scan

ATPG

RTL-to-GDS workflows

Synthesis/STA/Physical collaboration

Scripting (Python/Tcl/Perl)

Education

Bachelor's degree in Electrical/Computer Engineering or related

Tools

Siemens EDA

Synopsys

Cadence

Job description

Micron Technology, Inc. is seeking an experienced design-for-test (DFT) engineer to own SoC-level DFT architecture and implementation for high‑bandwidth memory (HBM) base‑die designs. You will work with RTL, synthesis, STA, and physical design teams to ensure manufacturability and silicon bring‑up.

This role requires hands‑on DFT expertise (scan, MBIST/LBIST, boundary scan/JTAG, ATPG), strong collaboration across global teams, and a drive to innovate for future HBM generations.