DFT Engineer (Design for Testability) - Staff

Micron Technology; Richardson (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

Micron Technology seeks a Staff DFT Design Engineer in Richardson, Texas to develop and integrate test architectures for next-generation High Bandwidth Memory (HBM) products. This key role involves collaborating with various engineering teams to ensure test coverage across multiple stages while balancing performance and cost.

The ideal candidate holds a degree in Electrical or Computer Engineering and has over five years of DFT design or verification experience. Skills in digital design fundamentals and familiarity with semiconductor test flows are essential.

Qualifications

• Strong grasp of digital design and DFT concepts.
• 5+ years DFT Design or Verification experience.

Responsibilities

• Define and implement HBM DFT architectures.
• Collaborate with Product Engineering and Test Enablement teams.
• Support silicon bring-up and qualification activities.

Skills

Digital design fundamentals

DFT concepts (scan, MBIST, boundary scan, JTAG)

RTL design (SystemVerilog/VHDL)

DRAM or ASIC DFT Design

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Summary

As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi‑functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions.

Responsibilities

• Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at‑speed test structures.
• Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements.
• Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows.
• Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets.
• Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon.
• Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is correctly implemented and verified.
• Collaborate with external partners and customers to align on custom DFT interfaces and security requirements when applicable.
• Support silicon bring‑up, debug, and qualification activities, including correlation between design intent and manufacturing test results.

Minimum Qualifications

• Bachelor’s degree or Master’s degree or equivalent experience in Electrical Engineering, Computer Engineering, or related field.
• Strong fundamentals in digital design and DFT concepts (scan, MBIST, boundary scan, JTAG).
• Experience with RTL design (SystemVerilog/VHDL) and logic integration.
• Familiarity with semiconductor test flows from wafer probe through final test.
• 5+ years DRAM or ASIC DFT Design or Verification experience.

Preferred Qualifications

• Experience with HBM, DRAM, or advanced memory products.
• Knowledge of TSV‑based 3D integration and stacked‑die test challenges.
• Hands‑on experience with at‑speed test, compression, or advanced DFT methodologies.
• Exposure to DFT security, customer‑specific DFT interfaces, or custom test modes.
• Structured problem‑solving and debug perspective.

Job Profile(s)

Semiconductor Design Engineer 4

Relocation Level

TBD

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.