Staff Signal Integrity Architect for AI Superchips

Arm; San Jose (CA); Vor Ort; USD 209.000 - 283.000; Vollzeit

Zusammenfassung

Arm is seeking a Staff Signal Integrity Engineer to lead design, modeling, and validation of high-speed interconnects for next-generation AI superchips and data-center platforms. The role spans silicon, advanced packaging, PCB, and system-level interconnects to ensure robust electrical performance and signaling reliability.

You will drive channel analysis for DDR5/LPDDR, PCIe/CXL, Ethernet, and SerDes, develop EM and IBIS models, and collaborate across teams to achieve design-for-sign-off.

Qualifikationen

• BS/MS/PhD in Electrical Engineering or related field.
• 8+ years in high-speed SI engineering, semiconductor packaging, or system-level electrical design.

Aufgaben

• Drive SI design, modeling, simulation, and validation across SoC, packaging, PCB, and system interconnects.
• Perform high-speed channel analysis and optimization for DDR5/LPDDR, PCIe/CXL, Ethernet, D2D, and SerDes interfaces.
• Develop and validate EM, S-parameter, IBIS/IBIS-AMI, and behavioral models for chip-to-chip and chip-to-memory interfaces.
• Lead SI optimization including insertion loss, return loss, crosstalk, impedance discontinuities, equalization, and BER-based eye-margin analysis.
• Collaborate with silicon PHY, package, PCB, architecture, and validation teams to drive SI design guidelines and SI-to-silicon correlation.
• Support advanced packaging technologies including chiplets, interposers, high-density substrates, and heterogeneous integration.

Kenntnisse

High-speed SI

SI design

3D electromagnetic modeling

Analytical problem-solving

Ausbildung

BS/MS/PhD in Electrical Engineering

Tools

Ansys HFSS

SIwave

Keysight ADS

Jobbeschreibung

Arm is seeking a Staff Signal Integrity Engineer to lead design, modeling, and validation of high-speed interconnects for next-generation AI superchips and data-center platforms. The role spans silicon, advanced packaging, PCB, and system-level interconnects to ensure robust electrical performance and signaling reliability.

You will drive channel analysis for DDR5/LPDDR, PCIe/CXL, Ethernet, and SerDes, develop EM and IBIS models, and collaborate across teams to achieve design-for-sign-off.