Senior Signal Integrity Engineer – AI Chip & 3D Packaging

Arm; Chandler (AZ); On-site; USD 209,000 - 283,000; Full time

Job summary

Arm is seeking a Staff Signal Integrity Engineer in the United States to lead SI design, modeling, and validation for AI superchip and data center platforms. You will work across silicon, advanced packaging, and system interconnects to ensure robust electrical performance.

The role requires 8+ years in high-speed SI, expertise with 3D EM tools such as HFSS, SIwave, and ADS, and a track record in DDR/LPDDR, PCIe/CXL, and SerDes interfaces.

Qualifications

• BS/MS/PhD in Electrical Engineering or related field.
• 8+ years in high-speed SI engineering, semiconductor packaging, or system-level electrical design.
• Strong expertise with SI simulation and 3D electromagnetic modeling tools.
• Solid understanding of high-speed I/O signaling, transmission lines, S-parameters, crosstalk, and BER analysis.

Responsibilities

• Drive SI design, modeling, simulation, and validation across SoC, 2.5D/3D packaging, PCB, and system interconnects.
• Perform high-speed channel analysis and optimization for DDR5/LPDDR, PCIe/CXL, Ethernet, D2D, and SerDes interfaces.
• Develop and validate EM, S-parameter, IBIS/IBIS-AMI, and behavioral models for chip-to-chip and chip-to-memory interfaces.
• Lead SI optimization including insertion loss, return loss, crosstalk, impedance discontinuities, equalization, and BER-based eye-margin analysis.
• Collaborate with silicon PHY, package, PCB, architecture, and validation teams to drive SI guidelines and sign-off.
• Support advanced packaging technologies including chiplets, interposers, high-density substrates, and heterogeneous integration.

Skills

SI design

3D EM modeling

High-speed I/O signaling

Signal integrity analysis

Cross-functional collaboration

Education

BS/MS/Ph.D. in Electrical Engineering

Tools

Ansys HFSS

SIwave

Keysight ADS

Job description

Arm is seeking a Staff Signal Integrity Engineer in the United States to lead SI design, modeling, and validation for AI superchip and data center platforms. You will work across silicon, advanced packaging, and system interconnects to ensure robust electrical performance.

The role requires 8+ years in high-speed SI, expertise with 3D EM tools such as HFSS, SIwave, and ADS, and a track record in DDR/LPDDR, PCIe/CXL, and SerDes interfaces.