Senior Signal Integrity Engineer for AI Superchips

ARM; United States; On-site; USD 209,000 - 283,000; Full time

Job summary

Arm is seeking an expert Staff Signal Integrity Engineer to drive SI design, simulation, optimization, and validation for AI Superchip and data center platforms. You will tackle high-speed interconnects across silicon, packaging, and system levels to ensure robust electrical performance.

Location options include Chandler, AZ or San Jose, CA, with collaboration across silicon PHY, packaging, PCB, and validation to deliver sign-off and design guidelines.

Qualifications

• BS/MS/Ph.D. in Electrical Engineering or a related field.
• 8+ years of experience in high-speed SI engineering, packaging, or system-level design.
• Strong expertise in SI simulation and 3D EM modeling tools.
• Experience with DDR/LPDDR memory interfaces, PCIe/CXL, and SerDes techs.
• Analytical, problem-solving and cross-functional collaboration skills.

Responsibilities

• Drive SI design, modeling, simulation, and validation across SoC, 2.5D/3D packaging, PCB, and system interconnects.
• Perform high-speed channel analysis and optimization for DDR5/LPDDR, PCIe/CXL, Ethernet, D2D, and SerDes.
• Develop and validate EM, S-parameter, IBIS/IBIS-AMI, and behavioral models for chip-to-chip and memory interfaces.
• Lead signal integrity optimization including insertion loss, return loss, crosstalk, impedance, equalization, and eye-margin analysis.
• Collaborate with silicon PHY, package, PCB, architecture, and validation teams to drive SI design guidelines and sign-off.
• Support advanced packaging tech including chiplets, interposers, and heterogeneous integration.

Skills

SI design

3D EM modeling

Channel modeling

DDR5/LPDDR

PCIe/CXL

Package interaction

Education

BS/MS/Ph.D. in Electrical Engineering

Tools

Ansys HFSS

SIwave

Keysight ADS

Job description

Arm is seeking an expert Staff Signal Integrity Engineer to drive SI design, simulation, optimization, and validation for AI Superchip and data center platforms. You will tackle high-speed interconnects across silicon, packaging, and system levels to ensure robust electrical performance.

Location options include Chandler, AZ or San Jose, CA, with collaboration across silicon PHY, packaging, PCB, and validation to deliver sign-off and design guidelines.