Staff Layout Designer: CMOS IC Layout Innovator

Micron Technology, Inc.

Richardson (TX)

On-site

USD 110,000 - 170,000

Full time

5 days ago
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Job summary

Micron Technology, Inc. in Richardson, TX seeks a design engineer to collaborate across Design Engineering, Product Engineering, Process Integration, Probe and Assembly to proactively design memory and storage products that optimize manufacturing functions and deliver best cost, quality, reliability and time-to-market.

You will apply CMOS circuit design and VLSI coursework, Cadence Virtuoso experience, and LVS/DRC knowledge to drive innovation across memory generations, while maintaining clear

Qualifications

  • B.S.EE degree with + 4 years of experience
  • M.S.EE degree with 2+ years of experience.
  • Coursework in CMOS Circuit Design and VLSI
  • Coursework that included crafting the physical layout of circuits
  • Knowledge and experience using Cadence Virtuoso
  • Excellent problem-solving and analytical skills
  • A self-motivated, hard-working team player who enjoys working with others.
  • Good communication and documentation skills
  • Drive innovation into the future Memory generation with a dynamic work environment.

Responsibilities

  • Support Design, Product, Process Integration, Probe and Assembly to design products optimizing cost, quality, reliability and time-to-market.

Skills

Problem solving
Analytical skills
Team player
Communication skills
Documentation skills
Self-motivated

Education

B.S.E.E.
M.S.E.E.

Tools

Cadence Virtuoso
Calibre LVS/DRC
AI-enabled layout tools

Job description

Micron Technology, Inc. in Richardson, TX seeks a design engineer to collaborate across Design Engineering, Product Engineering, Process Integration, Probe and Assembly to proactively design memory and storage products that optimize manufacturing functions and deliver best cost, quality, reliability and time-to-market.

You will apply CMOS circuit design and VLSI coursework, Cadence Virtuoso experience, and LVS/DRC knowledge to drive innovation across memory generations, while maintaining clear

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