Jr. FPGA Developer (Compute Test, North Reading)

Teradyne; North Reading (MA); On-site; USD 99,000 - 158,000; Full time

Benefits offered by this job

Health benefits

Retirement plan

Tuition assistance

Paid vacation

Job summary

Teradyne in North Reading, MA is seeking a Junior FPGA Engineer to support design and delivery of high-performance FPGA-based solutions at the heart of our test platforms. You will work with experienced engineers on high-speed interfaces, digital systems, and system-level constraints in a collaborative environment.

This role offers growth at the intersection of FPGA design, board-level hardware, and software integration, with onsite three days per week.

Qualifications

• 2+ years of hands-on FPGA design and development.
• Working knowledge of Verilog/SystemVerilog for design and debugging.
• Exposure to AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure.
• Understanding of digital design fundamentals and ability to interpret schematics.
• Some exposure to high-speed interfaces such as PCIe, DDR, SerDes, or similar technologies and familiarity with AXI4, USB, I2C, and SPI.
• Basic experience bringing up or debugging FPGA designs on hardware platforms.
• Basic TCL and Python scripting skills and experience with version control systems.
• Strong communication and collaboration skills, with an interest in developing system-level thinking.

Responsibilities

• Support FPGA design implementation and bring-up under the guidance of senior engineers.
• Develop FPGA logic for defined interfaces and subsystems as part of a larger design.
• Collaborate with hardware, software, systems, and design verification teams on system-level solutions.
• Support timing closure, resource optimization, lab bring-up, debugging, and basic root cause analysis using JTAG and lab instrumentation.
• Build and maintain TCL and Python scripts that support design and validation workflows.
• Partner in code reviews, design discussions, and PCB and system design decisions that affect FPGA performance.

Skills

FPGA design

Verilog/SystemVerilog

Python scripting

TCL scripting

JTAG debugging

Team collaboration

SystemVerilog UVM

Tools

Xilinx toolchain

Intel FPGA toolchains

Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne (http://www.teradyne.com/) companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

Teradyne's Compute Test Division develops advanced test solutions for next-generation silicon, including high-performance SoCs and accelerators powering modern compute and AI systems. We are seeking a Junior FPGA Engineer to support the design and delivery of high-performance FPGA-based solutions at the heart of our test platforms. This role offers the opportunity to grow at the intersection of FPGA design, board-level hardware, and system architecture while working alongside experienced engineers on high-speed interfaces, complex digital systems, and system-level constraints. Based on site in North Reading, Massachusetts, the position is expected to work in the office three days per week and collaborate across functions on solutions that directly affect the quality and performance of cutting-edge semiconductor devices.

• Support FPGA design implementation and bring-up under the guidance of senior engineers.
• Develop FPGA logic for defined interfaces and subsystems as part of a larger design.
• Collaborate with hardware, software, systems, and design verification teams on system-level solutions, simulations, and test coverage goals.
• Support timing closure, resource optimization, lab bring-up, debugging, and basic root cause analysis using JTAG and lab instrumentation.
• Build and maintain TCL and Python scripts that support design and validation workflows.
• Partner in code reviews, design discussions, and PCB and system design decisions that affect FPGA performance, building toward greater technical ownership over time.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

• 2+ years of hands-on experience in FPGA design and development.
• Working knowledge of Verilog/SystemVerilog for design and debugging.
• Exposure to AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure.
• Understanding of digital design fundamentals and the ability to interpret schematics.
• Some exposure to high-speed interfaces such as PCIe, DDR, SerDes, or similar technologies and familiarity with protocols such as AXI4, USB, I2C, and SPI.
• Basic experience bringing up or debugging FPGA designs on hardware platforms.
• Basic TCL and Python scripting skills and experience with version control systems.
• Strong communication and collaboration skills, with an interest in developing system-level thinking and the ability to debug across FPGA, board, and software boundaries.
• Preferred: coursework or project experience with SystemVerilog-based verification methodologies such as UVM; familiarity with FPGA SoCs and embedded processor subsystems; exposure to ATE or measurement equipment design; a basic understanding of signal integrity and high-speed serial interfaces; or familiarity with AI tools for engineering design.

We are only considering candidates local to the position location and are unable to provide relocation for this position.

This position is not eligible for visa sponsorship.

Compensation:

The base salary range for this role is $98,700 - $157,900. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Benefits:

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

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Current openings may involve access to export controlled technology and may be subject to export licensing requirements prior to employment. ATTENTION APPLICANTS WITH DISABILITIES: If you’re unable to access our on-line application due to a disability you may visit one of our locations or our Corporate Office at 600 Riverpark Drive, North Reading, MA and request a paper application form. In addition, you may also contact the HR Service Center at 978-370-3041 or contact them at [e-mail] for additional assistance. LitePoint, a Teradyne Company is an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, age, disability status, protected veteran status, or any other characteristic protected by law. We are a VEVRAA Federal Contractor.