Junior FPGA Engineer: Build High-Speed Test Platforms

Teradyne; Reading (MA); On-site; USD 99,000 - 158,000; Full time

Benefits offered by this job

Health benefits

Tuition assistance

Paid vacation

Job summary

Teradyne in North Reading, MA seeks a junior FPGA engineer to design and deliver high-performance FPGA-based solutions for test platforms. You will work with senior engineers on high-speed interfaces and system constraints.

You will apply Verilog/SystemVerilog, develop TCL/Python scripts, and collaborate across hardware, software, and verification teams. On-site three days a week, visa sponsorship not provided.

Qualifications

• 2+ years hands-on FPGA design and development.
• Experience with Verilog/SystemVerilog for design and debugging.
• Exposure to Xilinx (AMD) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure.
• Understanding of digital design fundamentals.
• Experience with high-speed interfaces and protocols (PCIe, DDR, SerDes, AXI4, USB, I2C, SPI).
• Basic TCL and Python scripting skills and version control experience.
• Strong communication and collaboration skills.
• Desirable: SystemVerilog-based verification methodologies such as UVM.

Responsibilities

• Support FPGA design implementation and bring-up under guidance of senior engineers.
• Develop FPGA logic for defined interfaces and subsystems as part of a larger design.
• Collaborate with hardware, software, systems, and design verification teams on system-level solutions and test coverage goals.
• Support timing closure, resource optimization, lab bring-up, debugging, and basic root cause analysis using JTAG and lab instrumentation.
• Build and maintain TCL and Python scripts that support design and validation workflows.
• Participate in code reviews and design discussions affecting FPGA performance.

Skills

FPGA design

Verilog/SystemVerilog

High-speed interfaces

SystemVerilog verification (UVM)

TCL/Python scripting

Tools

Xilinx Vivado

Intel Quartus

Job description

Teradyne in North Reading, MA seeks a junior FPGA engineer to design and deliver high-performance FPGA-based solutions for test platforms. You will work with senior engineers on high-speed interfaces and system constraints.

You will apply Verilog/SystemVerilog, develop TCL/Python scripts, and collaborate across hardware, software, and verification teams. On-site three days a week, visa sponsorship not provided.