Staff Formal Verification Engineer — RTL & Tools Lead

Synopsys; Sunnyvale (CA); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

Health benefits

Equity

Annual bonus

Job summary

Synopsys is seeking a Senior Formal Verification Engineer to lead deployments and optimize verification workflows for customer designs in Sunnyvale. You will diagnose tool performance issues, tailor methodologies, and train customers on new features, working closely with R&D to align product directions.

Strong RTL/Verilog/VHDL, scripting, and formal verification experience are required. You will engage with customers to drive adoption, reduce bottlenecks, and scale verification across SoCs,

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering from an accredited institution.
• 5-7 years of hands-on experience in RTL design or verification, deploying advanced verification methodologies in production environments.
• Deep understanding of formal verification applications including formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking.
• Strong grasp of hardware design languages like Verilog or VHDL and the ability to read and reason about micro-architecture and RTL implementations.
• Proficiency in Unix/Linux environments with scripting in Tcl, Perl, Python, and shell scripting (bash, csh) for automation and flow development.
• Experience with assertion-based verification is strongly preferred, prior hands-on use of formal verification tools is a significant plus.
• Exposure to verification consulting or managing verification responsibility for complex hardware designs is desirable.

Responsibilities

• Lead formal verification deployments with customers, assessing their design environments, verification gaps, and RTL complexity to recommend methodologies that actually fit their workflow
• Diagnose root causes of formal tool performance issues, whether it is state space explosion, over-constrained environments, or poorly scoped properties, and optimize formal testbenches and abstraction strategies to get results
• Identify which design blocks and verification scenarios are good candidates for formal property checking, sequential equivalence checking, connectivity checking, or formal coverage analysis
• Develop and deliver technical training on new formal features and product updates, translating release notes into practical guidance that helps customers adopt capabilities faster
• Work directly with Synopsys R&D and product engineering teams to communicate customer priorities, tool limitations, and feature requests that shape product roadmaps
• Support customers through complex formal runs, including data path logic verification, math function checks, and assertion-based verification integration
• Build reusable formal verification flows and best practices that scale across customer engagements and design types

Skills

RTL design

Formal verification

Verilog

VHDL

Unix/Linux

Python scripting

Tcl scripting

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Tools

Formal verification tools

RTL simulators

Job description

Synopsys is seeking a Senior Formal Verification Engineer to lead deployments and optimize verification workflows for customer designs in Sunnyvale. You will diagnose tool performance issues, tailor methodologies, and train customers on new features, working closely with R&D to align product directions.

Strong RTL/Verilog/VHDL, scripting, and formal verification experience are required. You will engage with customers to drive adoption, reduce bottlenecks, and scale verification across SoCs,