ASIC Verification Technical-Lead Engineer

Retym, Inc; Austin (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

Retym, Inc is seeking a Verification Team-Leader in Austin, Texas to drive the RTL design verification of next-generation high-speed communication technology. The successful candidate will lead a team, define verification strategies, and mentor engineers in a fast-paced startup environment.

With a minimum of 10 years in digital design verification and proven management experience, you will ensure project milestones are met while fostering a culture of excellence and innovation.

Qualifications

• 10+ years of experience in digital design verification.
• 3+ years of experience managing or leading verification teams.
• Proven track record of completing two or more full block/system verification cycles.
• Strong knowledge of VLSI verification flows, concepts and methodologies.

Responsibilities

• Lead and manage a team of verification engineers.
• Define and execute verification strategies for complex digital blocks.
• Oversee development of robust verification environments.
• Collaborate with design engineers to debug issues.
• Foster a culture of technical excellence within the team.

Skills

Digital design verification

Team leadership

Problem-solving

SystemVerilog

UVM

Tools

SystemVerilog

UVM

Python

Perl

Job description

For an exciting well‑funded start‑up, developing leading edge technology of the next generation high speed communication, we are looking for a Verification Team‑Leader to be driving into the complicated RTL design verification activity on various design aspects.

Key Responsibilities

• Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables.
• Define and execute verification strategies and plans for complex digital blocks and systems.
• Oversee the development of robust and reusable verification environments using SystemVerilog and UVM.
• Review and approve verification plans, testbenches, and coverage metrics.
• Drive functional and coverage‑based verification across multiple block/system verification cycles.
• Collaborate with design engineers to debug and resolve functionality issues.
• Ensure effective resource allocation and project planning to achieve optimal results.
• Foster a culture of technical excellence, continuous learning, and innovation within the team.
• Report verification progress, issues, and risks to senior management and other stakeholders.

Required Qualifications

• 10+ years of experience in digital design verification—a must.
• 3+ years of experience managing or leading verification teams.
• Proven track record of completing two or more full block/system verification cycles.
• In-depth knowledge of VLSI verification flows, concepts, methodologies and interfaces with algorithmic models and SW.
• Expertise in verification using SystemVerilog, UVM, or other industry‑standard methodologies (eRM, OVM).
• Experience in block, cluster and full chip verification levels.
• Strong problem‑solving skills and the ability to debug complex functionality issues.
• Excellent leadership, communication, and organizational skills to manage and inspire a team.

Preferred Qualifications

• Hands‑on experience with high‑speed communication protocols like Ethernet, PCIe, or SerDes.
• Proficiency in scripting languages (e.g., Python, Perl) for automation of verification processes.
• Familiarity with formal verification techniques and tools.
• Background in system‑level verification or post‑silicon validation.
• Experience with project planning tools and methodologies for effective team management.