Lead Formal Verification Engineer

Synopsys, Inc.; Sunnyvale (CA); Hybrid; USD 150,000 - 210,000; Full time

Job summary

Synopsys, Inc. in Sunnyvale, CA seeks a senior professional to lead formal verification deployments with customers, assess RTL complexity, and implement practical verification plans that fit workflows.

You will diagnose performance issues, optimize testbenches, and identify where formal methods provide the most value, while translating customer needs into actionable enhancements for R&D.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• 5-7 years hands-on RTL design or verification experience in production environments.
• Deep understanding of formal verification applications including property checking, equivalence checking, coverage analysis, and connectivity checking.
• Strong grasp of Verilog or VHDL and ability to read micro-architecture and RTL implementations.
• Proficiency in Unix/Linux with Tcl, Perl, Python, and shell scripting for automation.
• Experience with assertion-based verification; prior use of formal tools is a plus.
• Exposure to verification consulting or managing verification for complex hardware is desirable.

Responsibilities

• Lead formal verification deployments with customers, assessing design environments and RTL complexity to recommend fit-for-workflow methodologies.
• Diagnose root causes of formal tool performance issues and optimize testbenches and abstraction strategies.
• Identify design blocks suitable for formal checks and analysis techniques such as PC, SEC, connectivity, and coverage.
• Develop and deliver technical training on new formal features and product updates.
• Collaborate with R&D and product engineering to communicate priorities and feature requests.
• Support customers through complex runs including data-path logic verification and assertion-based verification integration.
• Build reusable formal verification flows and best practices for multiple engagements.

Skills

Formal verification

RTL design experience

Verilog/VHDL

Unix/Linux scripting

Assertion-based verification

Verification consulting

RTL complexity assessment

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Formal verification tools

Job description

Synopsys, Inc. in Sunnyvale, CA seeks a senior professional to lead formal verification deployments with customers, assess RTL complexity, and implement practical verification plans that fit workflows.

You will diagnose performance issues, optimize testbenches, and identify where formal methods provide the most value, while translating customer needs into actionable enhancements for R&D.