Staff Formal Verification Engineer - Customer-Facing

Synopsys; Sunnyvale (CA); On-site; USD 150,000 - 220,000; Full time

Job summary

Synopsys is seeking a skilled verification engineer to lead formal verification deployments with customers, assess RTL environments, and optimize methodologies. You’ll diagnose performance issues, identify suitable verification scenarios, and build reusable flows. Collaboration with R&D and product teams ensures roadmap alignment.

Strong training and communication skills are essential for success. You will work with design teams, read RTL, and push for practical, scalable verification strategies

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• 5–7 years hands-on experience in RTL design or verification.
• Deep understanding of formal verification applications including formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking.
• Strong grasp of Verilog or VHDL and ability to read micro-architecture and RTL implementations.
• Proficiency in Unix/Linux environments with scripting in Tcl, Perl, Python, and shell for automation and flow development.
• Experience with assertion-based verification is strongly preferred; prior hands-on use of formal verification tools is a plus.
• Exposure to verification consulting or managing verification responsibility for complex hardware designs is desirable.

Responsibilities

• Lead formal verification deployments with customers, assessing design environments and RTL complexity to recommend fit-for-workflow methodologies.
• Diagnose root causes of formal tool performance issues and optimize testbenches and abstractions to get results.
• Identify design blocks and verification scenarios for formal property checking, sequential equivalence checking, connectivity checking, or formal coverage analysis.
• Develop and deliver technical training on new formal features and product updates.
• Collaborate with R&D and product engineering to communicate customer priorities and shape roadmaps.
• Support customers through complex formal runs including data path logic verification and assertion-based verification integration.
• Build reusable formal verification flows and best practices scalable across engagements.

Skills

RTL verification

Verilog/VHDL

Unix scripting

Formal verification

Assertion-based verification

Education

Electrical/Computer Engineering degree

Job description

Synopsys is seeking a skilled verification engineer to lead formal verification deployments with customers, assess RTL environments, and optimize methodologies. You’ll diagnose performance issues, identify suitable verification scenarios, and build reusable flows. Collaboration with R&D and product teams ensures roadmap alignment.

Strong training and communication skills are essential for success. You will work with design teams, read RTL, and push for practical, scalable verification strategies