Staff Electromechanical Packaging Engineer

NAVITAS SEMICONDUCTOR USA, INC.

Torrance (CA)

In loco

USD 120.000 - 170.000

Tempo pieno

9 giorni fa

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Descrizione del lavoro

Navitas Semiconductor USA, Inc. seeks a Staff Electromechanical Packaging Engineer to join our fast-growing team. You will drive chip-scale packaging and HDI substrate layout for our voltage regulator product line, collaborating with substrate layout, ASIC, and manufacturing engineers.

You should have 3+ years in microelectronics packaging and be proficient with 3D CAD tools (Creo/NX/Catia). The role requires hands-on design, drawing creation, and interaction with OSAT suppliers to move from

Competenze

  • BS in Mechanical or Electrical engineering required.
  • 3+ years in microelectronics packaging.
  • Experience with substrate layout and HDI organic substrates.
  • Familiarity with DFx/DFM concepts.

Mansioni

  • Support chip-scale packaging design and HDI substrate layout for voltage regulator products.
  • Collaborate with substrate layout, ASIC design, and manufacturing engineers.
  • Create mechanical drawings for substrate fabrication and packaged parts.
  • Work with OSAT suppliers to baseline processes from prototype to mass production.

Conoscenze

3D CAD software
GD&T
Electrical schematics
Interconnect design
Thermal analysis basics
PCB design tools

Formazione

B.S. in EE
MS preferred

Strumenti

Creo
NX
Catia
Altium
Cadence
Mentor

Descrizione del lavoro

Job Purpose:Navitas Semiconductor (Nasdaq: NVTS) is a next-generation power semiconductor leader driving innovation in gallium nitride (GaN) and high-voltage silicon carbide (SiC) technologies. Our products enable faster, more efficient power delivery across AI data centers, high-performance computing, energy and grid infrastructure, and industrial electrification.With more than 30 years of combined expertise in wide bandgap technologies, GaNFast power ICs integrate GaN power, drive, control, sensing, and protection, delivering faster power delivery, higher system density, and greater efficiency. GeneSiC high-voltage SiC devices leverage patented trench-assisted planar technology to provide industry-leading voltage capability, efficiency, and reliability for medium-voltage grid and infrastructure applications.We are seeking a Staff Electromechanical Packaging Engineer to join our fast-growing, collaborative team. The ideal candidate is self-motivated, energetic, and able to thrive in a high-growth, innovative environment, contributing directly to technologies that are shaping the future of power electronics.Key Responsibilities and Duties:The Electromechanical Packaging Engineer will be working with a Lead Engineer and be responsible for:Support chip scale packaging design and HDI organic substrate layout for integrated voltage regulator product line.Collaborate with substrate layout, ASIC design, and manufacturing engineers.Create mechanical drawings for substrate fabrication and packaged part assembly. Work with vendors for components, assembly, and test.Work with OSAT (Out-Source Assembly and Test) suppliers in establishing process baseline from prototype to mass productionKnowledge, Skills, Abilities, and Other Characteristics (KSAO’s)Understanding of how electrical design requirements impact substrate layout and interconnect selectionProficient with 3D mechanical CAD software (Creo, NX, Catia, etc.), generating mechanical drawings, and GD&TAbility to read and create electrical schematicsFamiliarity with tape out processes for wafers and substrateBasic understanding of Form, Fit, Function elements in design for manufacturability (DFM).willingness to learn new concepts and techniques and conceptsFamiliarity with PCB design tools (Altium, Cadence, Mentor, etc.) is a plusBasic understanding of component level thermal analysis is a plusRequired QualificationsBasicMinimum BS in Mechanical or Electrical engineering, MS or higher-level degree preferred.3+ years’ experience with microelectronics packaging, and/or PCB designPreferredKnowledge of foundry processes and chip scale assembly processes
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