Staff CPU Physical Design Engineer — Lead PPA/EMIR

Google Inc.; Austin, Mountain View (TX, CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google Austin, TX, and Mountain View, CA, is seeking a Share Staff CPU Physical Design Engineer to lead end-to-end CPU design strategy for high-performance blocks. You will influence cross-functional teams across Architecture, RTL, DFT and Technology partners to optimize sub-systems for best PPA.

This role emphasizes solving complex timing, EMIR issues and driving roadmaps, with opportunities to mentor peers and shape future silicon architectures.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 10 years of experience in high-performance, low-power physical design implementation or design convergence techniques with synthesis, PnR and signoff tools.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with emphasis on computer architecture.

Responsibilities

• Lead end-to-end physical design strategy and execution for top-level and critical CPU blocks across advanced process nodes.
• Pioneer novel physical design methodologies, tool flows, and AI/ML optimization techniques to maximize power, performance, and area (PPA).
• Resolve complex timing, power grid, electromigration and IR drop (EMIR), and physical verification bottlenecks in tight iteration loops.
• Drive technical roadmaps, mentor executive engineering peers, and influence architectural trade-offs across cross-functional teams.

Skills

High-performance physical design

Synthesis/PnR/Signoff tools

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical/Computer Engineering or Computer Science (preferred)

Tools

Synthesis tools

PnR tools

Signoff tools

Job description

Google Austin, TX, and Mountain View, CA, is seeking a Share Staff CPU Physical Design Engineer to lead end-to-end CPU design strategy for high-performance blocks. You will influence cross-functional teams across Architecture, RTL, DFT and Technology partners to optimize sub-systems for best PPA.

This role emphasizes solving complex timing, EMIR issues and driving roadmaps, with opportunities to mentor peers and shape future silicon architectures.