CPU Physical Design Engineer

Google; Austin (TX); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is hiring for a senior block-level physical design engineer to develop custom silicon powering its products. You will work on high-performance, low-power architectures, collaborating with RTL, architecture, and DFT teams to meet tight parity and timing goals.

The role emphasizes signoff discipline, STA, physical verification, and QoR improvements to deliver efficientcompute blocks, with input on preferred working location from Austin, TX or Mountain View, CA.

Qualifications

• Bachelor’s degree or equivalent practical experience in EE/CS.
• 4 years of experience with digital physical design, synthesis, Place and Route (PnR), and timing closure.
• Experience in high-performance, low-power physical design implementation with industry standard tools.

Responsibilities

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.

Skills

Digital physical design

Synthesis

Place and Route (PnR)

Timing closure

Low-power design

Education

Bachelor's degree in EE/CE/CS or related field

Master's degree or PhD with emphasis on computer architecture

Tools

STA tools

Physical verification tools

Electrical checks tooling

Python scripting

Tcl scripting

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.


• 4 years of experience with digital physical design implementation, including synthesis, Place and Route (PnR), and timing closure.


• Experience in high-performance, low-power physical design implementation or design convergence with industry standard synthesis, PnR and signoff tools.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.


• Experience with Static Timing Analysis (STA), physical verification, or electrical checks using industry-standard tools.


• Experience working on high-performance CPU, GPU, or SoC block-level designs in advanced process nodes (e.g., 5nm or below).


• Proficiency in scripting with Tcl or Python for workflow automation and QoR analysis.


• Understanding of power grid design, EMIR constraints, and low-power implementation techniques.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.


• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.


• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.


• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .