Senior CPU Physical Design Engineer — AI/ML PPA

Google; Austin (TX); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google is seeking a seasoned hardware design leader to advance custom silicon. You will drive end-to-end physical design for top-level CPU blocks, pushing the boundaries of power, performance and area across cutting-edge process nodes.

You will collaborate with Architecture, RTL, DFT and Technology partners, mentoring peers and shaping architectural trade-offs. The role offers competitive compensation, equity, and comprehensive benefits.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in high-performance, low-power physical design implementation or design convergence techniques with custom or industry standard synthesis, PnR and signoff tools.

Responsibilities

• Lead end-to-end physical design strategy and execution for top-level and critical CPU blocks across advanced process nodes.
• Pioneer novel physical design methodologies, tool flows, and AI/ML optimization techniques to maximize power, performance, and area (PPA).
• Resolve complex timing, power grid, electromigration and IR drop (EMIR), and physical verification bottlenecks in tight iteration loops.
• Drive technical roadmaps, mentor executive engineering peers, and influence architectural trade-offs across cross-functional teams.

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science (emphasis on computer architecture)

Job description

Google is seeking a seasoned hardware design leader to advance custom silicon. You will drive end-to-end physical design for top-level CPU blocks, pushing the boundaries of power, performance and area across cutting-edge process nodes.

You will collaborate with Architecture, RTL, DFT and Technology partners, mentoring peers and shaping architectural trade-offs. The role offers competitive compensation, equity, and comprehensive benefits.