Staff CPU Physical Design Engineer

Google; Mountain View (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google in Mountain View, CA is seeking a senior electrical engineer to lead end-to-end physical design for CPU blocks, guiding tool flows and PPA optimizations across advanced nodes.

The role requires 10 years in high-performance, low-power design with synthesis, PnR, and signoff experience, and emphasizes cross-functional leadership across Architecture, RTL, and Technology teams.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of experience in high-performance, low-power physical design implementation or design convergence techniques with custom or industry standard synthesis, PnR and signoff tools.

Responsibilities

• Lead end-to-end physical design strategy and execution for top-level and critical CPU blocks across advanced process nodes.
• Pioneer novel physical design methodologies, tool flows, and AI/ML optimization techniques to maximize power, performance, and area (PPA).
• Resolve complex timing, power grid, electromigration and IR drop (EMIR), and physical verification bottlenecks in tight iteration loops.
• Drive technical roadmaps, mentor executive engineering peers, and influence architectural trade-offs across cross-functional teams.

Skills

Physical design

CPU design

PPA optimization

Leadership

Education

Bachelor's degree in EE/CE/CS

Master's or PhD (preferred)

Tools

Synthesis tools

PnR tools

Signoff tools

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in high-performance, low-power physical design implementation or design convergence techniques with custom or industry standard synthesis, PnR and signoff tools.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience leading cross-functional engineering initiatives across Architecture, RTL, DFT, and Technology partners to optimize sub-system microarchitecture.
• Understanding of power grid design, EMIR constraints, and low-power implementation techniques.
• Track record of architecting CPU class physical design methodologies, custom tool enhancements, or AI/ML-assisted PPA optimization flows.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Lead end-to-end physical design strategy and execution for top-level and critical CPU blocks across advanced process nodes.
• Pioneer novel physical design methodologies, tool flows, and AI/ML optimization techniques to maximize power, performance, and area (PPA).
• Resolve complex timing, power grid, electromigration and IR drop (EMIR), and physical verification bottlenecks in tight iteration loops.
• Drive technical roadmaps, mentor executive engineering peers, and influence architectural trade-offs across cross-functional teams.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .