CPU Physical Design Engineer for High-Perf SoC

Google; Mountain View (CA); On-site; USD 141,000 - 192,000; Full time

Job summary

Google is developing custom silicon to power our direct-to-consumer hardware. This role contributes to high-performance, low-power block designs for CPUs, GPUs, or SoCs, collaborating across RTL, Architecture, and DFT teams.

You will lead block-level implementation, signoff, and QoR analysis with emphasis on timing, power, and area in a fast-paced hardware environment based in Mountain View, CA or preferred location. Competitive compensation includes equity and bonus.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

Responsibilities

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.

Skills

Digital physical design

Synthesis

Place and Route (PnR)

Timing closure

Low-power design

Scripting: Tcl/Python

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering/Computer Science (computer architecture emphasis)

Tools

STA tools

Physical verification tools

Electrical checks

Job description

Google is developing custom silicon to power our direct-to-consumer hardware. This role contributes to high-performance, low-power block designs for CPUs, GPUs, or SoCs, collaborating across RTL, Architecture, and DFT teams.

You will lead block-level implementation, signoff, and QoR analysis with emphasis on timing, power, and area in a fast-paced hardware environment based in Mountain View, CA or preferred location. Competitive compensation includes equity and bonus.