Senior CPU Cache & Subsystem Design Lead

Google; Mountain View (CA); On-site; USD 240,000 - 333,000; Full time

Job summary

Google in Mountain View, CA is seeking a senior CPU design leader to drive end-to-end RTL development for next-generation CPU subsystems. You will lead front-end design and coordinate with arch, software, verification, and power teams to deliver high-performance, power-efficient RTL.

The role emphasizes micro-architecture evaluation, design option decisions, and a focus on load-store and cache subsystems to achieve PPA targets. Equity and bonus targets complement base pay.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including micro-architecture definition and PPA processing.
• Experience leading and managing teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Responsibilities

• Lead and manage a team of design engineers working on CPU functional units, emphasizing micro-architecture and RTL design for the next generation CPU subsystem.
• Review/propose performance enhancing micro-architecture features, and work with Software, Architect and Performance teams for trade-off studies. Communicate the pros and cons of micro-architecture enhancements.
• Deliver with plans on achieving project milestones and goals, towards a design that meets production quality on schedule.
• Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
• Focus on load-store-unit and cache subsystem design and optimizations with other parts of CPU to deliver best Performance, Power, Area (PPA).

Skills

CPU design

RTL design

team leadership

front-end checks

Education

Bachelor's degree in Electrical Engineering, Computer Science, or equivalent

Tools

RTL design tools

Job description

Google in Mountain View, CA is seeking a senior CPU design leader to drive end-to-end RTL development for next-generation CPU subsystems. You will lead front-end design and coordinate with arch, software, verification, and power teams to deliver high-performance, power-efficient RTL.

The role emphasizes micro-architecture evaluation, design option decisions, and a focus on load-store and cache subsystems to achieve PPA targets. Equity and bonus targets complement base pay.