Staff CPU Core Formal Verification Engineer

SiFive; California (MO); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Healthcare benefits

Retirement plans

Paid time off

Job summary

SiFive is seeking a Staff Design Verification Engineer to drive formal verification of high-performance CPU core functionality. This staff IC role is within the CPU Design Verification group, focused on applying formal methods to complex out-of-order microarchitecture.

The candidate should independently own difficult verification problems and improve verification quality across the CPU DV effort. The role requires strong experience with RTL formal verification, assertion-based techniques, and

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science.
• 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
• Direct experience with CPU/core verification.
• Strong hands-on experience with formal verification for RTL, including assertion-based verification, proof analysis, abstraction techniques, and closure of non-trivial properties.
• Experience developing assertions and formal strategies for control-heavy, ordering-sensitive, or interface-sensitive hardware behavior.
• Strong debugging skills with the ability to root-cause issues across specification, RTL, properties, and verification infrastructure.
• Strong understanding of verification methodology, including test planning, failure analysis, coverage thinking, and signoff discipline.
• Familiarity with scripting or programming in Python, Perl, Tcl, or similar languages used for automation and infrastructure.

Responsibilities

• Own formal verification planning and execution for one or more high-performance out-of-order CPU core areas, from block-level proof strategy through signoff-oriented closure.
• Develop formal verification plans based on architectural intent and microarchitectural risk, including assumptions, assertions, covers, abstraction strategy, and closure criteria.
• Create and maintain scalable formal environments, property sets, checkers, harnesses, and proof infrastructure for complex CPU control, ordering, and interface behavior.
• Target high-value CPU verification problems such as pipeline control, issue and dispatch correctness, flush and replay behavior, register/data movement correctness, load-store ordering, hazard handling, forward progress, and clock-gating correctness.
• Use the right mix of abstraction, decomposition, bounded proofs, connectivity checks, X-prop style reasoning, and bug-hunting strategies to improve proof convergence and debug efficiency.
• Analyze proof failures, counterexamples, vacuity, over-constraint, and incompleteness, and drive fixes across RTL, properties, assumptions, and verification infrastructure.
• Partner closely with architecture, RTL, and simulation-focused DV engineers to review specifications, identify ambiguities early, and align formal results with broader verification goals.
• Contribute reusable formal methodology, automation, debug workflows, and infrastructure that improve productivity and verification quality across future CPU core programs.
• Mentor other engineers through reviews, property-quality guidance, and formal-debug best practices.

Skills

Formal verification

CPU/core verification

RTL verification

Debugging

Scripting (Python, Tcl, Perl)

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Formal verification tools

RTL simulation tools

Scripting for automation

Job description

SiFive is seeking a Staff Design Verification Engineer to drive formal verification of high-performance CPU core functionality. This staff IC role is within the CPU Design Verification group, focused on applying formal methods to complex out-of-order microarchitecture.

The candidate should independently own difficult verification problems and improve verification quality across the CPU DV effort. The role requires strong experience with RTL formal verification, assertion-based techniques, and