Staff Design Verification Engineer – Formal CPU Core Expert

Sifive; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Equity

Healthcare benefits

Retirement plans

Job summary

SiFive is seeking a Staff Design Verification Engineer to drive formal verification for high-performance CPU core functionality. You will own planning, create scalable environments, and tackle complex verification challenges in collaboration with architecture and RTL teams.

The role emphasizes property-driven verification strategies, debugging efficiency, and advancing verification infrastructure for future CPU cores.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 7+ years of relevant experience in ASIC/CPU/core/SoC design verification with ownership for complex problems.
• Strong hands-on experience with formal verification for RTL, including assertion-based verification, proof analysis, and closure of non-trivial properties.
• Experience developing assertions and formal strategies for control-heavy, ordering-sensitive hardware behavior.
• Strong debugging skills to root-cause issues across specification, RTL, properties, and verification infrastructure.
• Familiarity with scripting or programming in Python, Perl, Tcl, or similar for automation and infrastructure.

Responsibilities

• Own formal verification planning and execution for high-performance out-of-order CPU core areas.
• Develop formal verification plans based on architectural intent and microarchitectural risk.
• Create and maintain scalable formal environments, property sets, checkers, harnesses, and proof infrastructure.
• Target high-value CPU verification problems such as pipeline control, issue and dispatch correctness, load-store ordering, and clock-gating correctness.
• Analyze proof failures, vacuity, and incompleteness, and drive fixes across RTL, properties, and infrastructure.
• Collaborate with architecture, RTL, and DV engineers to align formal results with verification goals.
• Contribute reusable formal methodology and automation to improve productivity and quality.

Skills

Formal verification

RTL verification

Assertion-based verification

CPU architecture knowledge

Python scripting

Debugging

Signoff discipline

Education

Electrical Engineering

Computer Engineering

Computer Science

Tools

Formal verification tools

Job description

SiFive is seeking a Staff Design Verification Engineer to drive formal verification for high-performance CPU core functionality. You will own planning, create scalable environments, and tackle complex verification challenges in collaboration with architecture and RTL teams.

The role emphasizes property-driven verification strategies, debugging efficiency, and advancing verification infrastructure for future CPU cores.