Staff CPU Core Formal Verification Engineer

SiFive; Santa Clara (CA); On-site; USD 130,000 - 190,000; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Job summary

SiFive is seeking a Staff Design Verification Engineer to drive formal verification of high-performance CPU core functionality. You will own verification strategy for out-of-order cores, develop plans with architectural intent, and build scalable environments for complex control, ordering, and interface behavior.

Collaborating with architecture, RTL, and DV engineers, you will tackle proofs for pipeline control, dispatch correctness, and clock-gating logic, mentoring peers and advancing

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification for a Staff role.
• Direct experience with CPU/core verification and solid understanding of computer architecture and CPU microarchitecture.
• Strong hands-on experience with formal verification for RTL, including assertion-based verification, proof analysis, abstraction techniques, and closure of non-trivial properties.
• Experience developing assertions and formal strategies for control-heavy, ordering-sensitive, or interface-sensitive hardware behavior.
• Strong debugging skills spanning specification, RTL, properties, and verification infrastructure.
• Familiarity with scripting or programming in Python, Perl, Tcl, or similar languages for automation.

Responsibilities

• Own formal verification planning and execution for one or more high-performance out-of-order CPU core areas, from block-level proof strategy to closure.
• Develop formal verification plans based on architectural intent and microarchitectural risk, including assumptions, assertions, covers, abstraction strategy, and closure criteria.
• Create and maintain scalable formal environments, property sets, checkers, harnesses, and proof infrastructure for complex CPU control, ordering, and interface behavior.
• Target high-value CPU verification problems such as pipeline control, issue and dispatch correctness, flush and replay behavior, register/data movement correctness, load-store ordering, hazard handling, forward progress, and clock-gating correctness.
• Use abstraction, decomposition, bounded proofs, connectivity checks, X-prop reasoning, and bug-hunting strategies to improve proof convergence and debug efficiency.
• Analyze proof failures, counterexamples, vacuity, over-constraint, and incompleteness, and drive fixes across RTL, properties, assumptions, and verification infrastructure.
• Partner with architecture, RTL, and simulation-focused DV engineers to align formal results with broader verification goals.
• Contribute reusable formal methodology, automation, debug workflows, and infrastructure to improve productivity and verification quality.
• Mentor other engineers through reviews, property-quality guidance, and formal-debug best practices.

Skills

Formal verification

CPU/core verification

ASIC/SoC design verification

Debugging

Scripting (Python Perl Tcl)

Education

Bachelor's or Master's degree in Electrical Engineering / Computer Engineering / Computer Science

Tools

RTL verification tooling

Job description

SiFive is seeking a Staff Design Verification Engineer to drive formal verification of high-performance CPU core functionality. You will own verification strategy for out-of-order cores, develop plans with architectural intent, and build scalable environments for complex control, ordering, and interface behavior.

Collaborating with architecture, RTL, and DV engineers, you will tackle proofs for pipeline control, dispatch correctness, and clock-gating logic, mentoring peers and advancing