Staff CPU Core Formal Verification Engineer

Socket.dev; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

SiFive is seeking a Staff Design Verification Engineer to drive formal verification of high-performance CPU core functionality and own verification planning for out-of-order cores.

The role emphasizes developing property-driven strategies, improving proof convergence, and mentoring other engineers within the CPU DV team. You will work closely with architecture, RTL, and simulation-focused DV engineers to deliver robust core designs.

Qualifications

• Bachelor’s or Master’s in EE/CE/CS.
• 7+ years of ASIC/CPU/SoC design verification experience for Staff level.
• Direct experience with CPU/core verification and RTL assertions.
• Strong debugging across specification, RTL, properties, and infra.
• Familiar with Python/Perl/Tcl for automation.

Responsibilities

• Own formal verification planning and execution for high-performance CPU core areas.
• Develop verification plans with architectural intent and risk-based strategies.
• Create and maintain scalable formal environments, property sets, and harnesses.
• Target verification problems: pipeline control, issue/dispatch, load-store ordering.
• Use abstraction, bounded proofs, and convergence strategies to improve proof quality.
• Analyze proof failures, vacuity, and incompleteness; drive fixes across RTL and infra.
• Collaborate with architecture, RTL, and DV engineers to align results with goals.
• Contribute reusable formal methodologies and debug workflows.
• Mentor engineers through reviews and best practices.

Skills

Formal verification

CPU/core verification

Debugging

RTL knowledge

Python/Perl/Tcl

Ownership

Mentoring

Signoff discipline

Architecture understanding

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

SiFive is seeking a Staff Design Verification Engineer to drive formal verification of high-performance CPU core functionality and own verification planning for out-of-order cores.

The role emphasizes developing property-driven strategies, improving proof convergence, and mentoring other engineers within the CPU DV team. You will work closely with architecture, RTL, and simulation-focused DV engineers to deliver robust core designs.