Staff CPU Core DV Engineer – ALU & Execution (Equity)

SiFive; Santa Clara (CA); On-site; USD 170,000 - 210,000; Full time

Job summary

SiFive is seeking a Staff Design Verification Engineer to drive verification of high-performance CPU core functionality, with focus on ALU and integer-execution microarchitecture. This role sits in the CPU Design Verification team and requires independent ownership of complex verification problems.

You will collaborate with architecture, RTL, performance, and verification teams to ensure design intent is captured, corner cases are validated, and signoff quality is achieved with scalable

Qualifications

• Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification, with strong hands-on ownership of complex verification problems appropriate for a Staff role.
• Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.
• Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.
• Experience verifying one or more CPU execution areas such as ALU pipelines, midcore execution/control logic, issue and dispatch behavior, dependency handling, forwarding, replay, or related integer-execution functionality.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debugging skills and the ability to translate architectural intent into effective verification strategy and execution.
• Familiarity with Python, C/C++, or similar scripting/programming languages used for DV infrastructure and automation.

Responsibilities

• Own verification planning and execution for ALU- and execution-focused CPU core functionality, from block-level verification through core-level integration and signoff.
• Drive verification strategy, test planning, debug, coverage analysis, and closure for complex execution-pipeline behaviors and microarchitectural interactions.
• Define effective verification approaches for challenging ALU-related behaviors such as arithmetic and logical execution correctness, compare and branch-condition generation, operand dependency handling, bypass and forwarding behavior, replay scenarios, flush and recovery interactions, exception behavior, and issue/dispatch to execute/commit pipeline interactions.
• Verify corner-case interactions between ALU execution and surrounding core logic, including scoreboarding, operand readiness, structural conflicts, speculative execution effects, and interaction with branch, load/store, and commit behavior.
• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
• Partner closely with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification completeness.
• Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
• Contribute reusable methodology, automation, and infrastructure that improve productivity and verification quality across future CPU core programs.
• Mentor other engineers through technical reviews, debugging guidance, and stronger verification practices.

Skills

SystemVerilog

CPU/core verification

Python/C/C++

Debugging

Test planning

Education

Bachelor's or Master’s in EE/CE/CS

Tools

Python

C/C++

Job description

SiFive is seeking a Staff Design Verification Engineer to drive verification of high-performance CPU core functionality, with focus on ALU and integer-execution microarchitecture. This role sits in the CPU Design Verification team and requires independent ownership of complex verification problems.

You will collaborate with architecture, RTL, performance, and verification teams to ensure design intent is captured, corner cases are validated, and signoff quality is achieved with scalable