Senior ASIC Verification Architect

Chelsea Search Group; Minneapolis (MN); On-site; USD 150,000 - 210,000; Full time

Job summary

Chelsea Search Group in Minneapolis, MN seeks a Lead Design Verification Engineer to architect UVM-based environments for digital SoCs and drive verification methodology, schedules, and staffing for a growing ASIC program. You will mentor engineers, own testplan development, coverage strategies, and sign-off criteria, while collaborating with design, validation, and customers.

Requires 8+ years of ASIC/SoC verification and strong SystemVerilog/UVM expertise, with US citizenship and ability to

Qualifications

• BS in Electrical/Computer Engineering or Computer Science.
• 8+ years of ASIC/SoC verification experience with ownership of a production tapeout.

Responsibilities

• Define and own ASIC verification methodology, standards, and sign-off criteria across company programs.
• Architect UVM-based verification environments for digital SoCs, memory subsystems, secure boot and cryptographic subsystems, and die-to-die interfaces.
• Establish reusable verification infrastructure — base classes, VIP strategy, scoreboarding and checker architecture, register abstraction (UVM RAL), and coverage models.
• Own verification planning: testplan development, coverage closure strategy, regression architecture, and sign-off metrics.
• Serve as the verification voice in design and architecture reviews, and as the technical interface to customers and stakeholders on verification approach and evidence.
• Onboard and mentor verification engineers; define team structure, roles, and hiring profiles; participate in recruiting and selection.
• Write SystemVerilog/UVM testbench code, sequences, agents, and coverage models; drive constrained-random verification to coverage closure; triage failures and root-cause.
• Support post-silicon bring-up by correlating silicon to pre-silicon models; maintain regression infrastructure, licenses, and CI for verification.

Skills

SystemVerilog

UVM

Constrained‑random

Functional coverage

SVA

RTL/Design intuition

Python

Perl

TCL

Shell

Git workflows

Linux

Leadership

Education

Bachelor's degree in EE/CE/CS

Tools

Synopsys VCS/Verdi

Cadence Xcelium

Siemens Questa

Job description

Chelsea Search Group in Minneapolis, MN seeks a Lead Design Verification Engineer to architect UVM-based environments for digital SoCs and drive verification methodology, schedules, and staffing for a growing ASIC program. You will mentor engineers, own testplan development, coverage strategies, and sign-off criteria, while collaborating with design, validation, and customers.

Requires 8+ years of ASIC/SoC verification and strong SystemVerilog/UVM expertise, with US citizenship and ability to