Senior ASIC Performance Architect & Modeling Lead

Meta

Phoenix (AZ)

On-site

USD 178,000 - 250,000

Full time

14 days+

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Job summary

Meta's Silicon Engineering team is seeking an ASIC Engineer focused on performance architecture and modeling. You will define architectural performance analysis, drive pre-silicon modeling, and explore microarchitectures for custom ASICs powering Meta's AI and data-center workloads.

You will collaborate with architecture, RTL, and software teams to ensure throughput, latency, and efficiency targets are met at hyperscale, and mentor peers in modeling techniques and calibration of models to

Qualifications

  • Bachelor's degree in a technical field or equivalent practical experience.
  • 8+ years of experience in ASIC design or silicon engineering.
  • 5+ years in ASIC performance modeling or pre-silicon simulation.
  • Proficiency in C++ and Python for modeling and tooling.
  • Experience with cycle-accurate or TL modeling using C++/SystemC.

Responsibilities

  • Define and own performance modeling strategy for custom ASICs using cycle-accurate and transaction-level simulations.
  • Drive microarchitectural exploration across compute, memory, interconnect, and I/O domains.
  • Develop and validate pre-silicon models predicting post-silicon behavior.
  • Create workloads/kernels for ML training/inference.
  • Establish performance analytics, benchmarking, and bottleneck identification.

Skills

C++
Python
SystemC
Cycle-accurate models
Pre-silicon modeling
Performance analysis
ASIC design
RTL collaboration
Assembly/Compiler

Education

Bachelor's degree in CS/CE

Tools

SystemVerilog
VHDL
SystemC

Job description

Meta's Silicon Engineering team is seeking an ASIC Engineer focused on performance architecture and modeling. You will define architectural performance analysis, drive pre-silicon modeling, and explore microarchitectures for custom ASICs powering Meta's AI and data-center workloads.

You will collaborate with architecture, RTL, and software teams to ensure throughput, latency, and efficiency targets are met at hyperscale, and mentor peers in modeling techniques and calibration of models to

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