ASIC Foundry & IP Engineer — High-Performance, Low-Power

Meta Careers; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is building custom silicon for AI infrastructure, seeking an ASIC Engineer to drive PPA analysis, test chip tapeouts, and high-density standard cell design with foundry partners. You will simulate transistor-level behavior, manage library characterization, and evaluate memory compilers for optimized performance and power.

A strong scripting background helps automate large-scale evaluations. Join Meta in Sunnyvale, contributing to next-generation AI workloads.

Qualifications

• 6+ years in a foundry team driving PPA analysis and benchmarking.
• Deep understanding of CMOS device physics and digital design.
• Proven track record in test chip tapeouts and end-to-end design ownership.

Responsibilities

• Analyze and benchmark foundry processes with physical design teams to pick optimal technologies.
• Run early PPA evaluations of foundation IP drops via preliminary PnR experiments.
• Architect and characterize high-density standard cell libraries with foundry partners.
• Run transistor-level simulations and manage automated library characterization flows.
• Evaluate memory compilers based on PPA and trade-off metrics.

Skills

CMOS physics

Digital circuit design

Test chip tapeouts

PPA analysis

Python scripting

Cadence Virtuoso

HSPICE/Spectre

Tools

Cadence Virtuoso

HSPICE

Spectre

PnR tools

Python/TCL/Perl/Skills

Job description

Meta is building custom silicon for AI infrastructure, seeking an ASIC Engineer to drive PPA analysis, test chip tapeouts, and high-density standard cell design with foundry partners. You will simulate transistor-level behavior, manage library characterization, and evaluate memory compilers for optimized performance and power.

A strong scripting background helps automate large-scale evaluations. Join Meta in Sunnyvale, contributing to next-generation AI workloads.