Director - STA

NXP Semiconductors; Austin (TX); On-site; USD 180,000 - 280,000; Full time

Job summary

NXP Semiconductors seeks a Static Timing Design Manager for its AI and Chip Engineering SoC Implementation team in Austin. You will lead timing activities for MPU SoCs, develop and verify STA constraints, and drive timing closure across subsystems and full SoCs.

You will collaborate with RTL/IP teams, architecture and DV/EDA vendors to improve timing flows and implement cutting-edge STA methodologies in fast-paced, advanced node projects.

Qualifications

• 15+ years of experience in Physical Design for complex SoCs.
• Experience with at least 3 years of STA lead roles.
• Excellent communication skills, both oral and written.
• Innovate and adapt to the rapid use of AI and agents in STA & PD domains.

Responsibilities

• Timing Analysis activities for MPU SoCs.
• Expertise in developing, implementing and verifying STA constraints
• Expertise in efficient closure of Subsystem as well as SoC-level timing
• In-depth knowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & Route
• Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes
• Contribute to timing flow and methodology improvements
• Collaborate with members of a global design team to complete large SoC (system-on-chip) projects.

Skills

Timing analysis

STA leadership

Cross-functional collaboration

Excellent communication

Education

BS or MS in Electrical or Computer Engineering

Tools

EDA tools

Job description

Business Line Description

AI and Chip Engineering SoC Implementation team is seeking a passionate technologist who thrives in solving complex problems for the role of Static Timing Design Manager. As STA Manager, you will be managing a team of motivated engineers working on the AI, Edge and Automotive Processors in NXP. You will be working on fast paced, and leading-edge advanced node technologies building exciting and complex SoCs. You will be a major influence in the development, and support of the SoC implementation organization’s charter to build world-class MPUs.

Job Summary

• Timing Analysis activities for MPU SoCs.
• Expertise in developing, implementing and verifying STA constraints
• Expertise in efficient closure of Subsystem as well as SoC-level timing
• In-depth knowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & Route
• Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes
• Contribute to timing flow and methodology improvements
• Collaborate with members of a global design team to complete large SoC (system-on-chip) projects.

Cross Functional Collaboration

• Partner with Architecture and RTL teams to influence early design decisions
• Ability to coordinate with all aspects of SOC design functions, including RTL, DV, DFT, EDA vendors, DTCO while setting technical direction for the team
• Work with methodology teams to continuously improve flows and processes

Key Challenges

• Demonstrate strong expertise in all aspects of timing analysis for a wide variety of designs, from constraint generation and verification to full-chip timing closure across all modes and scenarios.
• Deep understanding of advanced topics such as crosstalk, noise, OCV, timing margins.
• Familiarity with Clock specs, jitter, IR drop, spice analysis.
• Experience working with multi-site teams for execution is a must.

Job Qualifications

• BS or MS in Electrical or Computer Engineering
• 15+ years of experience in Physical Design for complex SoCs
• Experience with at least 3 years of STA Lead roles
• Excellent communication skills, both oral and written
• Innovate and adapt to the rapid use of AI and agents in STA & PD domains

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law.

In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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About NXP

NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com.

Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.

Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.

Thank you for considering a career at NXP.

Thank you for your interest in supporting our recruitment efforts. Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities. Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited. Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise.