SRAM Layout Design Engineer

Gdh Consulting, Inc.; Santa Clara (CA); On-site; USD 101,000 - 106,000; Full time

Benefits offered by this job

Medical insurance

Dental & Vision insurance

Life insurance

401(k)

Wellbeats membership

Gym membership discount

Job summary

GDH Consulting, Inc. is seeking a senior SRAM layout design engineer to take full ownership of the custom layout process for SRAM bitcell arrays, peripheries, and memory macros on advanced CMOS nodes.

The role emphasizes layout quality, parasitic control, and collaboration with circuit and CAD teams. You will develop floorplans, perform DRC/LVS/ERC checks, and support tapeout readiness, while mentoring junior engineers and refining layout methodologies.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• Over 10 years of IC layout experience with at least 5 years in SRAM/memory IP layout.
• Experience executing custom SRAM layouts, not just reviews.
• Deep experience with 3nm or newer nodes; 5nm a plus.
• Strong understanding of LOD, density, fill, masking, and electromigration.
• Proficiency in Cadence Virtuoso and DRC/LVS debugging with Calibre/ICV.
• Ability to collaborate with circuit, PnR, foundry, and CAD teams.
• Authorized to work in the United States without sponsorship.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, peripheries, test structures, and memory macros utilizing advanced CMOS technologies.
• Develop and optimize floorplans for memory arrays, including placement, power grid design, routing channels, and macro assembly.
• Perform, debug, and complete DRC/LVS/ERC and other checks with tools like Calibre and ICV.
• Support parasitic extraction, EM and IR drop analysis, power integrity, density/fill and layout‑dependent effects for tapeout.
• Collaborate with circuit designers to translate schematics into layouts with matching, symmetry, shielding and reliability.
• Coordinate with front‑end design, PnR and integration teams to resolve top‑level layout issues and pin access.
• Develop and refine layout methodologies, checklists, and best practices for high‑quality memory IP.
• Partner with foundry, CAD, and methodology teams to interpret design rules and constraints for advanced nodes.
• Review layouts and mentor junior engineers to raise layout quality and process rigor.

Skills

Strong communication

Mentorship

Ownership

Team collaboration

Education

Bachelor's degree in Electrical Engineering or equivalent

Tools

Cadence Virtuoso

Calibre

ICV

Job description

Role Summary

A senior-level SRAM layout design engineer with extensive experience in advanced CMOS technology nodes. This role involves full ownership of the custom layout process for SRAM memory components, including bitcell arrays, peripheries, test structures, and memory macros. The position offers the opportunity to work on cutting‑edge process nodes in a collaborative environment, contributing to high-quality memory IP development.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, peripheries, test structures, and memory macros utilizing advanced CMOS technologies.
• Develop and optimize floorplans for memory arrays, including placement, power grid design, routing channels, and macro assembly.
• Perform, debug, and complete design rule checks (DRC), layout versus schematic (LVS), electrical rule checks (ERC), antenna checks, and other physical verification tasks with tools such as Calibre and ICV.
• Support parasitic extraction, electromigration (EM) and IR drop analysis, power integrity, density/fill considerations, DFM, dummy insertion, and layout‑dependent effects to ensure successful tapeout.
• Collaborate with circuit designers to translate schematics into layouts, prioritizing matching, symmetry, shielding, parasitic control, and reliability constraints.
• Work with front‑end design, PnR, and integration teams to resolve top‑level layout issues, pin accessibility, routing, power delivery, and macro integration.
• Develop and refine layout methodologies, checklists, and best practices to ensure consistent delivery of high‑quality memory IP.
• Partner with foundry, CAD, and methodology teams to interpret design rules, process constraints, waivers, and rule deck behavior for advanced nodes.
• Review layouts, mentor junior engineers, and contribute to raising layout quality and process rigor across the team.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent technical field.
• Over 10 years of hands‑on IC layout experience, with at least 5 years dedicated to SRAM, memory compiler, or full‑custom memory IP layout.
• Proven experience directly executing custom digital SRAM layouts, rather than solely reviewing or overseeing layouts.
• Extensive experience with advanced process nodes at TSMC 3nm or more advanced - experience with 10nm or 7nm is insufficient; 5nm is a plus.
• Strong understanding of SRAM and memory layout principles, including layout‑dependent phenomena such as LOD, density, fill, masking, matching, and electromigration.
• Proficiency in Cadence Virtuoso for custom layout creation and assessment.
• Skilled in DRC/LVS debugging using tools like Calibre and ICV.
• Deep knowledge of floorplanning, block‑level routing, macro assembly, pin planning, and top‑level physical verification.
• Familiarity with advanced‑node layout limitations, including layout‑dependent effects such as IR drop and layout‑dependent variability.
• Ability to collaborate effectively with circuit teams, PnR teams, foundries, and CAD teams.
• Strong communication skills, ownership, judgment, and mentorship capabilities.
• In compliance with federal law, all persons hired must verify their identity and eligibility to work in the United States and complete the required employment eligibility verification form upon hire.
• Candidates must be legally authorized to work in the United States without employer sponsorship, now or in the future.

Employment Details

Publishing Pay Range: $73.50 - $77.00 hourly.

This position is based in office and requires employee to work on-site.

About GDH

At GDH, we believe in the power of people and the importance of caring. Our culture statement, "We care about people," isn't just a tagline - it's the core of everything we do. GDH is a premier staffing and talent solutions company dedicated to helping businesses find the best talent and assisting job seekers in finding their dream jobs.

Who We Are: GDH, founded in 2001, has grown into a leader in providing staffing solutions across various industries. We specialize in IT across several sectors, connecting top talent with leading enterprises. As a Best of Staffing firm recognized for excellence in client, employee, talent, and women's services, we pride ourselves on our commitment to quality and service.

GDH Benefits

• Our health benefits include three medical insurance options with access to KISx Card, Zero Card, and HealthJoy concierge services.
• Other plan offerings include dental, vision, life, disability, supplemental insurance, and pet insurance plans.
• Enjoy additional perks like holiday pay, 401(k) plan, direct deposit, an employee referral program, work‑life balance benefits, a Wellbeats membership, a discounted gym membership program, and more!
• For more detailed information on benefits, please go to GDH's website under the tab for candidates.

EEO Statement

GDH provides equal employment opportunities (EEO) to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, gender, sex (including pregnancy), sexual orientation, gender identity, national origin, age, disability, genetic information, marital status, ancestry, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable federal, state, and local laws. Applicants with disabilities who require an accommodation or assistance in applying and/or for interviewing, please contact our HR Department.

Notice

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