Staff DRAM Design Engineer - Architect & Validate Memory

Micron; Boise (ID); On-site; USD 120,000 - 170,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off program

Paid holidays

Job summary

Micron Technology is seeking a Staff DRAM Design Engineer to shape memory architectures and drive circuit innovations from concept to silicon validation. You will lead DRAM circuit design, optimize performance, power, and die size while collaborating with cross-functional teams to deliver impactful results.

The role requires hands-on circuit design, SPICE/Verilog analysis, and experience with memory architectures.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 2+ years of circuit design experience or 4+ years in product engineering.
• Strong understanding of analog and digital circuit fundamentals and debugging.
• Experience with circuit simulation tools and methodologies.
• Knowledge of CMOS behavior, timing, and performance optimization.

Responsibilities

• Lead design and optimization of DRAM circuits including memory array, control logic, datapath, and test logic.
• Perform and analyze circuit simulations using SPICE and Verilog.
• Evaluate architectural trade-offs impacting power, performance, and die size.
• Integrate layout parasitics into simulations and drive design for manufacturability.
• Define validation strategies including test chip development and silicon bring-up.

Skills

Circuit design

Circuit simulations

CMOS fundamentals

Cross-functional communication

Education

Bachelor’s degree in Electrical Engineering

Tools

SPICE

Verilog

Job description

Micron Technology is seeking a Staff DRAM Design Engineer to shape memory architectures and drive circuit innovations from concept to silicon validation. You will lead DRAM circuit design, optimize performance, power, and die size while collaborating with cross-functional teams to deliver impactful results.

The role requires hands-on circuit design, SPICE/Verilog analysis, and experience with memory architectures.