Sr. Staff ASIC Design Engineer

Advanced Micro Devices, Inc.; San Jose (CA); Hybrid; USD 150,000 - 190,000; Full time

Benefits offered by this job

AMD Benefits at a glance

Job summary

Advanced Micro Devices, Inc. in San Jose, CA is seeking a hardware design engineer to contribute to FPGA product development within the AECG group.

You will participate in RTL development, implement complex digital and mixed-signal blocks, and collaborate with cross-functional teams across time zones to deliver silicon and software solutions. The role requires strong Verilog/SystemVerilog RTL experience, proficiency with UVM-based verification, and scripting in Python/Perl/Tcl/Shell.

Qualifications

• Bachelor's or Master's degree in computer engineering, electrical engineering, or related field.
• Strong RTL design using Verilog/SystemVerilog.
• Experience with UVM-based verification.
• Proficiency in scripting languages (Python, Perl, Tcl, Shell).
• Excellent written and verbal English; cross-functional collaboration.

Responsibilities

• Participate in RTL development through GDS implementation.
• Design RTL for digital and mixed-signal blocks using Verilog and SystemVerilog.
• Support physical design activities: synthesis, DFT, place-and-route, STA.
• Collaborate with Verification teams for block-level verification using SystemVerilog/UVM.
• Develop/design automation tooling with Perl, Tcl, Shell, Python.
• Partner with cross-functional teams across locations.
• Communicate with global project teams to meet milestones.

Skills

Verilog

SystemVerilog

RTL design

UVM

Python

Perl

Tcl

Shell scripting

Education

Bachelor's or Master's degree in electrical/computer engineering or related field

Tools

Synopsys DC Compiler

Primetime

VCS

Cadence Virtuoso

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

As a key member of AMD’s FPGA Product and Platform development team, you will have various responsibilities in the technical execution of Adaptive & Embedded Computing Group (AECG) device programs from definition to productization. You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting IP development for Silicon implementation and first-time-right SW solution.

THE PERSON

You are passionate about HW architecture, Digital design, and building cutting-edge silicon. As a strong problem solver and analytical thinker, you bring collaboration, communication, and adaptability to cross-functional teams spanning multiple time zones.

KEY RESPONSIBILITIES:

• Participate in all stages of the design flow, from RTL development through GDS implementation.
• Design and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.
• Support physical design activities, including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
• Collaborate closely with Functional Verification teams to support block-level verification using constrained-random and directed test environments based on System Verilog and UVM.
• Utilize scripting languages such as Perl, Tcl, Shell, and Python to maintain existing design automation flows and develop new tools supporting various aspects of design implementation.
• Partner with cross-functional teams across multiple engineering disciplines and geographic locations.
• Communicate regularly with global project teams to resolve technical issues and ensure project milestones and objectives are achieved.

PREFERRED EXPERIENCE:

• Strong understanding of different design stages from RTL to GDS implementation
• Proficient in RTL design implementation of Digital/Analog blocks using Verilog/System Verilog. Experience with HBM, D2D, Serdes, PCIe like protocols.
• Knowledge in VLSI design, Design Automation, and IC design.
• Knowledge of Physical Design (floor planning, synthesis, place & route) and Static Timing Analysis.

• Basic knowledge of EDA Tools (like Synopsys DC Compiler, Primetime, VCS, Cadence Virtuoso).
• Experience with UVM/OVM and/or Verilog, System Verilog test benches, BFMs and usage of simulation tools/debug environments is preferred.
• Basic understanding of FPGA architecture and customer usage model is a plus.
• Proficiency in Perl, Tcl, Shell, Python and/or other scripting language.
• Excellent written and verbal communication skills in English.
• Self-motivated team worker with ability to work in a fast-paced work environment.

ACADEMIC CREDENTIALS:

• Bachelor's or master's degree in computer engineering, electrical engineering, or a related field.

LOCATION:

San Jose, CA (Hybrid)

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.