Sr. RTL Design Engineer

AMD; San Jose (CA); Hybrid; USD 140,000 - 210,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD's FPGA Product and Platform development team in San Jose, CA is seeking a skilled engineer to drive RTL design and implementation for complex digital blocks. You will work across physical design, verification, and software tooling to deliver silicon and first-time-right software solutions.

You will design RTL using Verilog/SystemVerilog, support synthesis, place-and-route, and STA, and collaborate with global teams across time zones. Strong scripting in Python/Perl/Tcl is valued.

Qualifications

• Bachelor's or master's degree in electrical or computer engineering.
• Strong RTL design and integration experience using Verilog and SystemVerilog.
• Experience with high-speed interfaces and complex IPs (HBM, PCIe, SerDes).
• Familiarity with industry EDA tools and design automation.

Responsibilities

• Participate in all stages of the design flow from RTL development through GDS implementation.
• Design and implement RTL for complex digital/mixed-signal blocks using Verilog and SystemVerilog.
• Support physical design activities: synthesis, DFT implementation, place-and-route, STA.
• Collaborate with verification teams using UVM, constrained-random testing, and BFMs.
• Develop and maintain design automation tooling with Python, Tcl, Shell, and Perl.

Skills

RTL Design

Verilog/SystemVerilog

DFT/STA

UVM verification

Scripting (Python, Perl, Tcl, Shell)

Synthesis & STA

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys DFT Compiler

TestMAX

PrimeTime

VCS

Cadence tool suites

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

ROLE:

As a key member of AMD’s FPGA Product and Platform development team, you will have various responsibilities in the technical execution of Adaptive & Embedded Computing Group (AECG) device programs from definition to productization. You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting IP development for Silicon implementation and first-time-right SW solution.

THE PERSON

You are passionate about HW architecture, Digital design, and building cutting-edge silicon. As a strong problem solver and analytical thinker, you bring collaboration, communication, and adaptability to cross-functional teams spanning multiple time zones.

KEY RESPONSIBILITIES:

• Participate in all stages of the design flow, from RTL development through GDS implementation.
• Design and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.
• Support physical design activities, including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
• Collaborate closely with Functional Verification teams to support block-level verification using constrained-random and directed test environments based on System Verilog and UVM.
• Utilize scripting languages such as Perl, Tcl, Shell, and Python to maintain existing design automation flows and develop new tools supporting various aspects of design implementation.
• Partner with cross-functional teams across multiple engineering disciplines and geographic locations.
• Communicate regularly with global project teams to resolve technical issues and ensure project milestones and objectives are achieved.

PREFERRED EXPERIENCE:

• Strong understanding of the complete ASIC/SoC development flow, from RTL architecture through physical implementation and silicon bring-up.
• Strong RTL design and integration experience using Verilog and SystemVerilog.
• Experience working with high-speed interfaces and complex IPs such as HBM, Die-to-Die (D2D), SerDes, PCIe, and memory subsystems.
• Deep understanding of VLSI design principles, Design Automation methodologies, and IC development processes.
• Working knowledge of physical design concepts including floorplanning, synthesis, place-and-route, timing closure, and Static Timing Analysis (STA).
• Hands-on experience with industry-standard EDA tools such as Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence tool suites.
• Experience with UVM/OVM verification methodologies, testbench development, BFMs, simulation environments, and debug workflows.
• Proven experience implementing DFT solutions for large-scale SoCs, including scan, compression, MBIST, LBIST, boundary scan, and related test technologies.
• Familiarity with FPGA architectures and prototyping methodologies is a plus.
• Strong scripting and automation skills using Perl, Tcl, Shell, Python, or similar languages.
• Demonstrated ability to independently drive technical initiatives and solve complex engineering challenges.
• Excellent written and verbal communication skills, with the ability to effectively collaborate across geographically distributed teams.
• Proven ability to mentor engineers and contribute to technical leadership within an organization.

ACADEMIC CREDENTIALS:

Bachelor's or master’s degree in electrical engineering, computer engineering, or a related field.

LOCATION:

San Jose, CA (Hybrid)

#LI-MV1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.