Sr DRAM Layout Engineer - Analog Blocks & IP

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 80,000 - 100,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid family leave

Robust paid time-off program

Paid holidays

Job summary

1000 Micron Technology, Inc. in Boise, Idaho, is seeking a Layout Engineer to design high-quality physical layouts for DRAM technologies. This role requires experience with Cadence Virtuoso and knowledge of verification methods such as DRC and LVS.

Candidates should have a strong grasp of analog layout fundamentals and experience with critical analog blocks. The position offers comprehensive benefits, including medical, dental, vision, and paid time off.

Qualifications

• Experience performing physical layout using Cadence Virtuoso or similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Good understanding of circuit-design principles to create high-performance layouts.

Responsibilities

• Design and develop IP layouts used in DRAM chips.
• Perform layout verification such as LVS, DRC, and quality checks.
• Deliver block-level layouts on time with acceptable quality.

Skills

Physical layout using Cadence Virtuoso

DRC and LVS verification

Circuit-design principles

Analog layout fundamentals

Job description

1000 Micron Technology, Inc. in Boise, Idaho, is seeking a Layout Engineer to design high-quality physical layouts for DRAM technologies. This role requires experience with Cadence Virtuoso and knowledge of verification methods such as DRC and LVS.

Candidates should have a strong grasp of analog layout fundamentals and experience with critical analog blocks. The position offers comprehensive benefits, including medical, dental, vision, and paid time off.