Senior DRAM Layout Engineer – Global IP Design

Micron Technology, Inc; Boise (ID); On-site; USD 80,000 - 100,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid family leave

Robust paid time-off program

Job summary

Micron Technology, Inc is seeking a Layout Engineer in Boise, Idaho. This role involves designing high-quality physical layouts for DRAM technologies and managing multiple projects while collaborating with global teams.

The ideal candidate should have experience in Cadence Virtuoso and a solid understanding of analog layout fundamentals. Micron offers comprehensive benefits including healthcare plans, paid time-off, and professional growth opportunities.

Qualifications

• Experience performing physical layout using Cadence Virtuoso or similar tools.
• Good understanding of Circuit Design principles for performance optimization.
• Hands-on experience in Critical Analog Layout design of various blocks.

Responsibilities

• Design and develop IP layouts for DRAM chips.
• Perform layout verification like LVS/DRC/EM.
• Guide and lead team members in layout execution.

Skills

Cadence Virtuoso

DRC

LVS

Analog Layout fundamentals

Critical Analog Layout design

Job description

Micron Technology, Inc is seeking a Layout Engineer in Boise, Idaho. This role involves designing high-quality physical layouts for DRAM technologies and managing multiple projects while collaborating with global teams.

The ideal candidate should have experience in Cadence Virtuoso and a solid understanding of analog layout fundamentals. Micron offers comprehensive benefits including healthcare plans, paid time-off, and professional growth opportunities.